LPC2926_27_29 NXP Semiconductors, LPC2926_27_29 Datasheet - Page 17

The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2

LPC2926_27_29

Manufacturer Part Number
LPC2926_27_29
Description
The LPC2926/2927/2929 combine an ARM968E-S CPU core with two integrated TCMblocks operating at frequencies of up to 125 MHz, Full-speed USB 2
Manufacturer
NXP Semiconductors
Datasheet
NXP Semiconductors
LPC2926_27_29
Product data sheet
Fig 4.
AHB MULTILAYER MATRIX
AHB TO APB BRIDGES
FLASH/SRAM/SMC
peripheral subsystem
SYSTEM CONTROL
USB REGISTERS
LPC2926/2927/2929 overview of clock areas
EVENT ROUTER
TIMER 0/1/2/3
general subsytem
GPIO0/1/2/3/5
UART0/1
SPI0/1/2
GPDMA
WDT
CFID
VIC
CPU
Two of the base clocks generated by the CGU0 are used as input into a second,
dedicated CGU (CGU1). The CGU1 uses its own PLL and fractional dividers to generate
two base clocks for the USB controller and one base clock for an independent clock
output.
BASE_SYS_CLK
CGU0
branch
clocks
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 28 September 2010
BA SE_ICLK0_CLK
BASE_ICLK1_CLK
BASE_IVNSS_CLK
BASE_MSCSS_CLK
BASE_PCR_CLK
ARM9 microcontroller with CAN, LIN, and USB
branch
branch
clocks
clock
branch
branch
clocks
clocks
LPC2926/2927/2929
modulation and sampling
BASE_USB_I2C_CLK
networking subsystem
CGU1
power control subsystem
control subsystem
ACCEPTANCE
BASE_USB_CLK
TIMER0/1 MTMR
BASE_OUT_CLK
RESET/CLOCK
GENERATION &
MANAGEMENT
GLOBAL
PWM0/1/2/3
FILTER
ADC0/1/2
CAN0/1
LIN0/1
I2C0/1
POWER
QEI
branch
branch
branch
clock
clock
clock
© NXP B.V. 2010. All rights reserved.
002aae146
CLOCK
OUT
USB
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