CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 8

IC SAMPLE RATE CONVERTER 28SOIC

CS8420-CSZ

Manufacturer Part Number
CS8420-CSZ
Description
IC SAMPLE RATE CONVERTER 28SOIC
Manufacturer
Cirrus Logic Inc
Type
Sample Rate Converterr
Datasheets

Specifications of CS8420-CSZ

Package / Case
28-SOIC
Applications
CD-R, DAT, DVD, MD, VTR
Mounting Type
Surface Mount
Operating Supply Voltage
5 V
Operating Temperature Range
- 10 C to + 70 C
Mounting Style
SMD/SMT
Resolution
17 bit to 24 bit
Control Interface
3 Wire, Serial
Supply Voltage Range
4.75V To 5.25V
Audio Ic Case Style
SOIC
No. Of Pins
28
Bandwidth
20kHz
Rohs Compliant
Yes
Audio Control Type
Volume
Dc
0841
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1782 - EVALUATION BOARD FOR CS8420
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1125-5

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS8420-CSZ
Manufacturer:
CIRRUS
Quantity:
319
Part Number:
CS8420-CSZ
Manufacturer:
CIRRUS
Quantity:
9 908
Part Number:
CS8420-CSZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS8420-CSZ/D1
Manufacturer:
CIRRUS
Quantity:
378
Part Number:
CS8420-CSZR
Manufacturer:
NICHICON
Quantity:
4 200
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI MODE
VA+ = VD+ = 5V ±5%, Inputs: Logic 0 = 0V, Logic 1 = VD+; C
Notes: 9. If Fso or Fsi is lower than 46.875 kHz, then maximum CCLK frequency should be less than 128Fso and
8
CCLK Clock Frequency
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
CCLK Falling to CDOUT Stable
Rise Time of CDOUT
Fall Time of CDOUT
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For f
less than 128Fsi. This is dictated by the timing requirements necessary to access the Channel Status
and User Bit buffer memory. Access to the control register file can be carried out at the full 6 MHz rate.
The minimum allowable input sample rate is 8 kHz, so choosing CCLK of less than or equal to
1.024 MHz should be safe for all possible conditions
sck
<1 MHz.
Parameter
CDOUT
CDIN
CCLK
CS
t css
t r2
Figure 3. SPI Mode Timing
t dsu
(Note 10)
t scl
(Note 11)
(Note 11)
t f2
(Note 9)
t sch
t dh
L
= 20 pF)
Symbol
t pd
t
f
t
t
t
t
t
t
csh
sch
dsu
t
t
sck
css
t
t
scl
dh
pd
r1
f1
r2
f2
Min
1.0
20
66
66
40
15
0
-
-
-
-
-
t csh
Typ
-
-
-
-
-
-
-
-
-
-
-
-
Max
100
100
6.0
(T
45
25
25
-
-
-
-
-
-
A
CS8420
= 25 °C;
DS245PP2
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s

Related parts for CS8420-CSZ