CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 16

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

2 bits of this register form the integer part of the ra-
tio, while the lower 6 bits form the fractional part.
Since, in many instances, Fso is known, this allows
the calculation of the incoming sample rate by the
host microcontroller.
6.
A 3-wire serial audio input port and a 3-wire serial
audio output port is provided. Each port can be ad-
justed to suit the attached device via control regis-
ters. The following parameters are adjustable:
master or slave, serial clock frequency, audio data
resolution, left or right justification of the data rel-
ative to left/right clock, optional 1 bit cell delay of
the 1st data bit, the polarity of the bit clock and the
polarity of the left/right clock. By setting the appro-
priate control bits, many formats are possible.
Figure 16 shows a selection of common input for-
mats, along with the control bit settings. The clock-
ing of the input section of the CS8420 may be
derived from the incoming ILRCK word rate clock,
using the on-chip PLL. The PLL operation is de-
scribed in the AES receiver description on page 19.
In the case of use with the serial audio input port,
the PLL locks onto the leading edges of the ILRCK
clock.
Figure 17 shows a selection of common output for-
mats, along with the control bit settings. A special
AES3 direct output format is included, which al-
lows serial output port access to the V, U, and C
bits embedded in the serial audio data stream. The
16
THREE-WIRE SERIAL AUDIO
PORTS
P bit is replaced by a bit indicating the location of
the start of a block. This format is only available
when the serial audio output port is being clocked
by the AES3 receiver recovered clock. Also, the re-
ceived channel status block start signal is only
available in hardware mode 5, as the RCBL pin.
In master mode, the left/right clock and the serial
bit clock are outputs, derived from the appropriate
clock domain master clock.
In slave mode, the left/right clock and the serial bit
clock are inputs. The left/right clock must be syn-
chronous to the appropriate master clock, but the
serial bit clock can be asynchronous and discontin-
uous if required. By appropriate phasing of the
left/right clock and control of the serial clocks,
multiple CS8420’s can share one serial port. The
left/right clock should be continuous, but the duty
cycle does not have to be 50%, provided that
enough serial clocks are present in each phase to
clock all the data bits. When in slave mode, the se-
rial audio output port must be set to left justified or
I
When using the serial audio output port in slave
mode with an OLRCK input which is asynchro-
nous to the port’s data source, then an interrupt bit
is provided to indicate when repeated or dropped
samples occur.
The CS8420 allows immediate mute of the serial
audio output port audio data via a control register
bit.
2
S data.
CS8420
DS245PP2