CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 41

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

11.17 Channel Status Data Buffer Control (18)
BSEL
CBMR
DETCI
EFTCI
CAM
CHS
DS245PP2
7
0
0 - Data buffer address space contains Channel Status data (default)
1 - Data buffer address space contains User data
0 - Allow D to E buffer transfers to overwrite the first 5 bytes of channel status data
1 - Prevent D to E buffer transfers from overwriting first 5 bytes of channel status data
0 - Allow C-data D to E buffer transfers (default)
1 - Inhibit C-data D to E buffer transfers
0 - Allow C-data E to F buffer transfers (default)
1 - Inhibit C-data E to F buffer transfers
0 - One byte mode
1 - Two byte mode
0 - Channel A information is displayed at the EMPH pin and in the receiver channel
1 - Channel B information is displayed at the EMPH pin and in the receiver channel
Selects the data buffer register addresses to contain User data or Channel Status data
Control for the first 5 bytes of channel status “E” buffer
D to E C-data buffer transfer inhibit bit.
E to F C-data buffer transfer inhibit bit.
C-data buffer control port access mode bit
Channel select bit
6
0
(default)
status register. Channel A information is output during control port reads when
CAM is set to 0 (One Byte Mode)
status register. Channel B information is output during control port reads when
CAM is set to 0 (One Byte Mode)
BSEL
5
CBMR
4
DETCI
3
EFTCI
2
CAM
1
CS8420
CHS
0
41