CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 51

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

14.2.1 Pin Description - Hardware Mode 1
Overall Device Control:
DFC0, DFC1 - Data Flow Control Inputs
S/AES - Serial Audio or AES3 Input Select
MUTE - Mute Output Data Input
OMCK - Output Section Master Clock Input
AES3/SPDIF Receiver Interface:
RXP, RXN - Differential Line Receiver Inputs
RMCK - Input Section Recovered Master Clock Output
RERR - Receiver Error Indicator
EMPH/U - Pre-emphasis Indicator Output or U-bit Data Input
DS245PP2
DFC0 and DFC1 inputs determine the major data flow options available in hardware mode, according to
Table 3.
S/AES is connected to ground in hardware mode 1, in order to select the AES3 input.
If MUTE is low, audio data is passed normally. If MUTE is high, then both the AES3 transmitted audio
data and the serial audio output port data is set to digital zero.
Output section master clock input. The frequency must be 256x the output sample rate (Fso).
Differential line receiver inputs, carrying AES3 type data.
Input section recovered master clock output. Will be at a frequency of 256x the input sample rate (Fsi).
This is also a start-up option pin, and requires a pull-up or pull-down resistor.
When high, indicates a problem with the operation of the AES3 receiver. The status of this pin is
updated once per sub-frame of incoming AES3 data. Conditions that cause RERR to go high are: parity
error, and bi-phase coding error, as well as loss of lock in the PLL. This is also a start-up option pin,
and requires a pull-up or pull-down resistor.
The EMPH/U pin reflects either the state of the EMPH channel status bits in the incoming AES3 type
data stream, or is the serial U-bit input for the AES3 type transmitted data, clocked by OLRCK. When
indicating emphasis EMPH/U is low if the incoming data indicates 50/15
otherwise.
s pre-emphasis and high
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