CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 15

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

5.
Multirate digital signal processing techniques are
used to conceptually upsample the incoming data
to very high rate and then downsample to the out-
going rate, resulting in a 24 bit output, regardless of
the width of the input. The filtering is designed so
that a full input audio bandwidth of 20 kHz is pre-
served if the input sample and output sample rates
are greater than 44.1 kHz. When the output sample
rate becomes less than the input sample rate, the in-
put is automatically bandlimited to avoid aliasing
products in the output. Careful design ensures min-
imum ripple and distortion products are added to
the incoming signal. The SRC also determines the
ratio between the incoming and outgoing sample
rates, and sets the filter corner frequencies appro-
priately. Any jitter in the incoming signal has little
impact on the dynamic performance of the rate con-
verter, and has no influence on the output clock.
5.1
When using the AES3 input, and when using the
serial audio input port in left justified and I
modes, all input data is treated as 24-bits wide. Any
truncation that has been done prior to the CS8420
to less than 24-bits should have been done using an
appropriate dither process. If the serial audio input
port is used to feed the SRC, and the port is in right
justified mode, then the input data will be truncated
to the SIRES bit setting value. If SIRES bits are set
to 16 or 20-bits, and the input data is 24-bits wide,
then truncation distortion will occur. Similarly, in
any serial audio input port mode, if an inadequate
number of bit clocks are entered (say 16 instead of
20), then the input words will be truncated, causing
truncation distortion at low levels. In summary,
there is no dithering mechanism on the input side of
the CS8420, and care must be taken to ensure that
no truncation occurs.
Dithering is used internally where appropriate in-
side the SRC block.
DS245PP2
SAMPLE RATE CONVERTER (SRC)
Dither
2
S
The output side of the SRC can be set to 16, 20 or
24 bits. Optional dithering can be applied, and is
automatically scaled to the selected output word
length. This dither is not correlated between left
and right channels. It is recommended that the dith-
er control bit be left in its default on state.
5.2
The SRC calculates the ratio between the input
sample rate and the output sample rate, and uses
this information to set up various parameters inside
the SRC block. The SRC takes some time to make
this calculation. For a worst case 3:1 to 1:3 input
sample rate transition, the SRC will take 9400/Fso
to settle (195 ms at Fso of 48 kHz). For a power-up
situation, the SRC will start from 1:1, the worst
case time becomes 8300/Fso (172 ms at Fso of
48 kHz).
If the PLL is in use (either AES3 or serial input
port), then the worst case locking time for the PLL
and the SRC is the sum of each locking time.
If Fsi is changing, for example in a varispeed appli-
cation, the REUNLOCK interrupt will occur, and
the SRC will track the incoming sample rate. Dur-
ing this tracking mode, the SRC will still rate con-
vert the audio data, but at increased distortion
levels. Once the incoming sample rate is stable,
then the REUNLOCK interrupt will become false,
and the SRC will return to normal levels of audio
quality.
The VFIFO interrupt occurs if the data buffer in the
SRC overflows, which can occur if the input sam-
ple rate changes at >10%/second.
Varispeed at Fsi slew rates approaching 10%/sec is
only supported when the input is via the serial au-
dio input port. When using the AES3 input, high
frame rate slew rates will cause the PLL to lose
lock.
The sample rate ratio is also made available as a
register, accessible via the control port. The upper
SRC Locking, Varispeed and the
Sample Rate Ratio Register
CS8420
15