CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 46

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

13. SOFTWARE MODE - PIN DESCRIPTION
The above diagram and the following pin descriptions apply to software mode. In hardware
mode, some pins change their function as described in subsequent sections of this data sheet.
Fixed function pins are marked with a *, and will be described once in this section. Pins marked
with a + are used upon reset to select various start-up options, and require a pull-up or pull-
down resistor.
Power Supply Connections:
VD+ - Positive Digital Power *
VA+ - Positive Analog Power *
DGND - Digital Ground *
AGND - Analog Ground *
Clock Related Pins:
OMCK - Output Section Master Clock Input
RMCK - Input Section Recovered Master Clock Output
FILT - PLL Loop Filter *
46
Positive supply for the digital section. Nominally +5V.
Positive supply for the analog section. Nominally +5V. This supply should be as quiet as possible since
noise on this pin will directly affect the jitter performance of the recovered clock.
Ground for the digital section. DGND should be connected to the same ground as AGND.
Ground for the analog section. AGND should be connected to the same ground as DGND.
Output section master clock input. The frequency must be 256x, 384x, or 512x the output sample rate
(Fso).
Input section recovered master clock output. Will be at a frequency of 128x or 256x the input sample
rate (Fsi).
An RC network should be connected between this pin and ground. Recommended schematic and
component values are given in the Receiver section of this data sheet.
CS8420
DS245PP2