CS8420-CSZ Cirrus Logic Inc, CS8420-CSZ Datasheet - Page 67

• Manufacturer Part Number: CS8420-CSZ
• Description: IC SAMPLE RATE CONVERTER 28SOIC
• Manufacturer: Cirrus Logic Inc
• Type: Sample Rate Converterr

Specifications of CS8420-CSZ

• Package / Case: 28-SOIC
• Applications: CD-R, DAT, DVD, MD, VTR
• Mounting Type: Surface Mount
• Operating Supply Voltage: 5 V
• Operating Temperature Range: - 10 C to + 70 C
• Mounting Style: SMD/SMT
• Resolution: 17 bit to 24 bit
• Control Interface: 3 Wire, Serial
• Supply Voltage Range: 4.75V To 5.25V
• Audio Ic Case Style: SOIC
• No. Of Pins: 28
• Bandwidth: 20kHz
• Rohs Compliant: Yes
• Audio Control Type: Volume
• Dc: 0841
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1782 - EVALUATION BOARD FOR CS8420
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 598-1125-5

14.7 Hardware Mode 6 Description
(AES3 Transmitter Only)
Hardware Mode 6 data flow is shown in Figure 31.
Audio data is input via the serial audio input port
and routed to the AES3 transmitter.
The transmitted channel status, user and validity
data may be input in 2 alternative methods, deter-
mined by the state of the CEN pin. Mode 6A is se-
lected when the CEN pin is low. In mode 6A, the
user data and validity bit are input via the U and V
pins, clocked by both edges of ILRCK. The chan-
nel status data is derived from the state of the
COPY/C, ORIG, EMPH, and AUDIO pins. Table
13 shows how the COPY/C and ORIG pins map to
channel status bits. In consumer mode, the trans-
mitted category code shall be set to Sample Rate
Converter (0101100).
Mode 6B is selected when the CEN pin is high. In
mode 6B, the channel status, user data and validity
bit are input serially via the COPY/C, U and V pins.
These pins are clocked by both edges of ILRCK (if
DS245PP2
ILRCK
ISCLK
SDIN
Power supply pins (VD+, VA+, DGND, AGND) & the reset pin (RST)
are omitted from this diagram. Please refer to the Typical Connection Diagram for hook-up details.
VD+
Figure 31. Hardware Mode 6 - AES3 Transmitter Only
APMS
DFC0
Serial
Audio
Input
SFMT1 SFMT0
VD+
DFC1
VD+
S/AES
COPY/C ORIG EMPH AUDIO TCBL
VD+
H/S
the port is in master mode). Figure 22 shows the
timing requirements.
The channel status block pin (TCBL) may be an in-
put or an output, determined by the state of the
TCBLD pin. The serial audio input port data format
is selected as shown in Table 14, and may be set to
master or slave by the state of the APMS input pin.
The following pages contain the detailed pin de-
scriptions for hardware mode 6.
COPY/C ORIG
SFMT1 SFMT0
Table 14. HW 6 Serial Audio Port Format Selection
Table 13. HW 6C COPY/C and ORIG pin function
0
0
1
1
0
0
1
1
C, U, V Data Buffer
FILT
0
1
0
1
0
1
0
1
PRO=0, COPY=0, L=0
PRO=0, COPY=0, L=1
PRO=0, COPY=1, L=0
PRO=1
Serial Input Format IF1
Serial Input Format IF2
Serial Input Format IF3
Serial Input Format IF4
Output
Clock
Source
AES3
Encoder
& Tx
OMCK
TCBLD
Function
Function
TXP
TXN
CEN
U
V
CS8420
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