AD9239 Analog Devices, AD9239 Datasheet - Page 6

• Manufacturer Part Number: AD9239
• Description: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9239

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 250MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9239
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, T
otherwise noted.
Table 4.
Parameter
CLOCK
DATA OUTPUT PARAMETERS
TERMINATION CHARACTERISTICS
APERTURE
OUT-OF-RANGE RECOVERY TIME
1
2
3
See the
Receiver dependent.
See the
Clock Rate
Clock Pulse Width High (t
Clock Pulse Width Low (t
Data Output Period or UI
Data Output Duty Cycle
Data Valid Time
PLL Lock Time (t
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
Data Rate per Channel (NRZ)
Deterministic Jitter
Random Jitter
Channel-to-Channel Bit Skew
Channel-to-Channel Packet Skew
Output Rise/Fall Time
Differential Termination Resistance
Aperture Delay (t
Aperture Uncertainty (Jitter)
(DOUT + x, DOUT − x)
AN-835
Digital Start-Up Sequence
1
Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and details on how these tests were completed.
LOCK
A
)
)
EL
EH
)
)
2
section.
3
MIN
Temp
Full
Full
Full
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
= −40°C, T
Min
170
2.65
2.65
MAX
AD9239BCPZ-170
= +85°C, 1.25 V p-p differential input, AIN = –1.0 dBFS, DCS enabled, unless
50
2.72
0
50
100
0.2
Typ
2.9
2.9
1/(16 × f
0.8
4
250
50
10
6
+1
1.2
1
CLK
Rev. B | Page 6 of 40
)
Max
100
40
Min
210
2.15
2.15
AD9239BCPZ-210
Typ
2.4
2.4
1/(16 × f
50
0.8
4
250
50
3.36
10
6
0
+1
50
100
1.2
0.2
1
CLK
)
Max
100
40
Min
250
1.8
1.8
AD9239BCPZ-250
Typ
2.0
2.0
1/(16 × f
50
0.8
4
250
50
4.0
10
6
0
+1
50
100
1.2
0.2
1
CLK
)
Max
100
40
Unit
MSPS
ns
ns
sec
%
UI
μs
ns
μs
CLK cycles
Gbps
ps max
ps rms
sec
CLK cycles
ps
Ω
ns
ps rms
CLK cycles