AD9239 Analog Devices, AD9239 Datasheet - Page 26

• Manufacturer Part Number: AD9239
• Description: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9239

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 250MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9239
Scramblers
There are three scramblers on the AD9239. The scramblers are
an Ethernet scrambler (x
x
in the packet). The scramblers are used to help balance the number
of 1s and 0s in the packet.
The Ethernet and SONET scramblers work on scrambling the
whole packet (64 bits), the header and the data (56 bits), or just
the data (48 bits). The scrambler is self-synchronizing on the
descramble end or receive end and does not require an additional
sync bit. For a copy of either the Ethernet or SONET scrambler
code, send an email to [e-mail].
Figure 65 and Figure 66 show the serial implementation of the
Ethernet and SONET scramblers. The parallel implementation
allows the scrambler and descrambler to run at a slower clock
rate and can be implemented in the fabric of a receiver.
The serial implementations of the Ethernet and SONET scramblers
more easily show what is being done. The parallel implementation
must be derived from the serial implementation. The end product
depends on how many bits need to be processed in parallel. For
the scrambler, 64 bits are processed even in the 56- and 48-bit
cases. To achieve this for 56 bits and 48 bits, a portion of two
samples is used to fill the rest of the input word.
Inverter Balance Example
The inverter implementation uses predetermined bit positions
to balance the packet in an overrange condition (all 1s or all 0s)
in the converter. The inversions are present in all conditions,
not just the overrange condition.
The descrambler can be based off any number of bits the user
chooses to process. In the inverter-based scrambler, the packet
6
+ 1), and a static inverter scrambler (inverts bits at set locations
58
+ x
39
+ 1), a SONET scrambler (x
7
Rev. B | Page 26 of 40
+
is balanced based on an overranged condition. If each packet is
balanced, the bit stream should be balanced. Instead of a random
sequence that changes from packet to packet, certain inverts are
set at predetermined bit positions within the packet. This allows
the decoding to be done in the receiver end. Figure 67 shows the
inverters in the packet for the 12-bit data case and the inverter
order in the header.
Table 12 shows the average value of the packet for various
conditions.
Table 12. Average of 1s and 0s in Overrange Conditions
Assuming Header Bits are All 0
No Scramble (Data = 0)
No Scramble (Data = 1)
Average of Negative and Positive
Scramble Only Data (Data = 0)
Scramble Only Data (Data = 1)
Average of Negative and Positive
Scramble Data and Header (Data = 0)
Scramble Data and Header (Data = 1)
Average of Negative and Positive
If the analog signal is out of range, there should be about the same
number of out-of-range positive and out-of-range negative values.
The average for no scrambling and for scrambling just the data
is about the same. If the header is used to indicate out of range,
the balance improves for the 12-bit case.
Overrange
Overrange
Overrange
12-Bit
0
0.844
0.422
0.375
0.469
0.422
0.437
0.531
0.484
ECC
00000000
00000000
00111111
00000000
00111111
00111111