AD9239 Analog Devices, AD9239 Datasheet - Page 37

• Manufacturer Part Number: AD9239
• Description: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9239

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 250MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

Power and Ground Recommendations
When connecting power to the AD9239, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the printed circuit board (PCB) level and close to the
parts, with minimal trace lengths.
A single PCB ground plane should be sufficient when using the
AD9239. With proper decoupling and smart partitioning of the
analog, digital, and clock sections of the PCB, optimum
performance can easily be achieved.
Rev. B | Page 37 of 40
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the best
electrical and thermal performance of the AD9239. An exposed
continuous copper plane on the PCB should mate to the AD9239
exposed paddle, Pin 0. The copper plane should have several vias
to achieve the lowest possible resistive thermal path for heat
dissipation to flow through the bottom of the PCB. These vias
should be solder-filled or plugged with nonconductive epoxy.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the ADC and PCB during the reflow
process, whereas using one continuous plane with no partitions
guarantees only one tie point. See Figure 79 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see the
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package (LFCSP), at www.analog.com.
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 79. Typical PCB Layout
AN-772 Application
AD9239
Note,