AD9239 Analog Devices, AD9239 Datasheet - Page 30

• Manufacturer Part Number: AD9239
• Description: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9239

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 250MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9239
TEMPOUT Pin
The TEMPOUT pin can be used as a course temperature sensor
to monitor the internal die temperature of the device. This pin
typical has a 734 mV output with a clock rate of 250 MSPS and
a negative temperature going coefficient of −1.12 mV/C. The
voltage response of this pin is characterized in Figure 76.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) between ground and the RBIAS pin.
The resistor current is derived on chip and sets the AVDD current
of the ADC to a nominal 725 mA at 250 MSPS. Therefore, it is
imperative that a 1% or less tolerance on this resistor be used to
achieve consistent performance.
VCMx Pins
The common-mode output pins can be enabled through the SPI
to provide an external reference bias voltage of 1.4 V for driving the
VIN + x/VIN − x analog inputs. These pins may be required when
connecting external devices, such as an amplifier or transformer,
to interface to the analog inputs.
RESET Pin
The RESET pin sets all SPI registers to their default values and
the datapath. Using this pin requires the user to resync the
digital outputs. This pin is only 1.8 V tolerant.
PDWN Pin
When asserted high, the PDWN pin turns off all the ADC
channels, including the output drivers. This function can be
changed to a standby function. See Register 8 in Table 15. Using
this feature allows the user to put all channels into standby mode.
The output drivers transmit pseudorandom data until the outputs
are disabled using Register 14.
By asserting the PDWN pin high, the AD9239 is placed into
power-down mode, shutting down the reference, reference buffer,
PLL, and biasing networks. In this state, the ADC typically
dissipates 3 mW. If any of the SPI features are changed before
0.85
0.83
0.81
0.79
0.77
0.75
0.73
0.71
0.69
0.67
0.65
–40 –30 –20 –10
Figure 76. TEMPOUT Pin Voltage vs. Temperature
0
TEMPERATURE (°C)
10
20
30
40
50
60
70
80
Rev. B | Page 30 of 40
the power-down feature is enabled, the chip continues to function
after PDWN is pulled low without requiring a reset. The AD9239
returns to normal operating mode when the PDWN pin is pulled
low. This pin is only 1.8 V tolerant.
SDO Pin
The SDO pin is for use in applications that require a 4-wire SPI
mode operation. For normal operation, it should be tied low to
AGND through a 10 kΩ resistor. Alternatively, the device pin
can be left open, and the 345 Ω internal pull-down resistor pulls
this pin low. This pin adheres to only 1.8 V logic.
SDI/SDIO Pin
The SDI/SDIO pin is for use in applications that require either a
4- or 3-wire SPI mode operation. For normal operation, it should
be tied low to AGND through a 10 kΩ resistor. Alternatively,
the device pin can be left open, and the 30 kΩ internal pull-
down resistor pulls this pin low. This pin is only 1.8 V tolerant.
SCLK Pin
For normal operation, the SCLK pin should be tied to AGND
through a 10 kΩ resistor. Alternatively, the device pin can be left
open, and the 30 kΩ internal pull-down resistor pulls this pin low.
This pin is only 1.8 V tolerant.
CSB Pin
For normal operation, the CSB pin should be tied high to
AVDD through a 10 kΩ resistor. Alternatively, the device pin
can be left open, and the 26 kΩ internal pull-up resistor pulls
this pin high. By tying the CSB pin to AVDD, all SCLK and
SDI/SDIO information is ignored. In comparison, by tying the
CSB pin low, all information on the SDO and SDI/SDIO pins
are written to the device. This feature allows the user to reduce
the number of traces to the device if necessary. This pin is only
1.8 V tolerant.
PGMx Pins
All PGMx pins are automatically initialized as a sync pin by
default. These pins are used to lock the FPGA timing and data
capture during initial startup. These pins are respective to each
channel (PGM3 = Channel A). The sync pin should be pulled
low until this pin receives a high signal input from the receiver,
during which time the ADC outputs a training word. The training
word defaults to the values implemented by the user in Register 19
through Register 20. When the receiver finds the frame boundary,
the sync identification is deasserted high and the ADC outputs
the valid data on the next packet boundary.
Once steady state operation for the device has occurred, these
pins can be assigned as a standby option using Register 53 in
Table 15. All other pins change to a global sync pin.
This pin is only 1.8 V tolerant.