AD9239 Analog Devices, AD9239 Datasheet
AD9239
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AD9239 Summary of contents
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... BUF VIN – D VCM D RBIAS TEMPOUT Fabricated on an advanced CMOS process, the AD9239 is avail- able in a Pb-free/RoHS-compliant, 72-lead LFCSP package specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. Four ADCs are contained in a small, space-saving package. ...
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... AD9239 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 AC Specifications .......................................................................... 4 Digital Specifications ................................................................... 5 Switching Specifications .............................................................. 6 Timing Diagram ........................................................................... 7 Absolute Maximum Ratings ............................................................ 8 Thermal Resistance ...................................................................... 8 ESD Caution .................................................................................. 8 Pin Configuration and Function Description .............................. 9 REVISION HISTORY 5/10—Rev Rev. B Changes to Table 15 .................................................................. 35, 36 2/10— ...
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... AD9239 Max Unit Bits ± ±0.6 LSB ±1.3 LSB 1 kΩ MHz 1 mV/°C mV μA 1.9 V 1.9 V 775 ...
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... Full 10.2 10.4 10.1 25°C 25°C 10.3 25°C Full 87.5 78.6 25°C 25°C 82 25°C Full 79 74 25°C 25°C 84 25°C Full 96 86 25°C 25°C 88 25°C 78 25°C Rev Page AD9239BCPZ-250 Typ Max Min Typ Max 64.5 64.2 63.1 64.1 63.9 63.2 63.3 64.2 63.9 62.8 63.8 63.1 63 63.1 10.4 10.3 10.1 10.3 4 10.2 10 ...
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... AVDD 0.2 × AVDD 0 0 −60 − AVDD + 1.2 0.3 0.3 0 Current Current mode mode logic logic 0.8 0.8 DRVDD/2 DRVDD/2 AD9239 Max Unit 6 V p-p AVDD + V 1.6 V AVDD V 3.6 V 0.8 V +10 μA +10 μA 24 kΩ 0.2 × V AVDD μA μA μA μA kΩ ...
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... CLK 50 50 0.8 0 250 250 2.72 3. 100 100 1.2 1.2 0.2 0 Rev Page AD9239BCPZ-250 Max Min Typ Max 100 250 100 1.8 2.0 1.8 2.0 ) 1/(16 × CLK CLK 50 0.8 4 250 4 100 1.2 0.2 1 Unit MSPS ns ns sec ...
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... DATA PACKET 1 (64 BITS) 8-BIT HEADER 48-BIT ADC CHANNEL ID DATA-WORD Figure 2. Timing Diagram Bits[44:33] Bits[32:21] Data 2 Data 3 (12 bits MSB first) (12 bits MSB first) Rev Page ... ... ... ... 8-BIT ERROR CORRECTION Bits[20:9] Bits[8:1] Data 4 ECC (12 bits MSB first) (8 bits MSB first) AD9239 ...
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... AD9239 ABSOLUTE MAXIMUM RATINGS Table 6. Parameter Electrical AVDD to AGND DRVDD to DRGND AGND to DRGND AVDD to DRVDD DOUT ± DRGND SDO, SDI/SDIO, CLK± , VIN ± x, VCMx, TEMPOUT, RBIAS to AGND SCLK, CSB, PGMx, RESET, PDWN to AGND Environmental Storage Temperature Range Operating Temperature Range ...
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... ADC D True Digital Output. ADC D Complement Digital Output. ADC C True Digital Output. ADC C Complement Digital Output. ADC B True Digital Output. ADC B Complement Digital Output. ADC A True Digital Output. ADC A Complement Digital Output. Power-Down. Rev Page AD9239 PGM0 52 PGM1 51 PGM2 50 ...
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... AD9239 Pin No. Mnemonic 37 SDO 38 SDI/SDIO 39 SCLK 40 CSB 44 VIN + A 45 VIN − VCM A 50 PGM3 51 PGM2 52 PGM1 53 PGM0 56 VCM B 58 VIN − VIN + B 67 VIN + C 68 VIN − VCM 19, 36, NC 49, 54, 63, 72 Description Serial Data Output. Used for 4-wire SPI interface. ...
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... SNR = 64.62dB ENOB = 10.44 BITS SFDR = 75.48dBc 100 FREQUENCY (MHz) = 10.3 MHz SAMPLE 0 AIN = –1.0dBFS SNR = 64.50dB ENOB = 10.42 BITS SFDR = 77.97dBc 100 FREQUENCY (MHz) = 84.3 MHz SAMPLE AD9239 100 = 210 MSPS 120 = 250 MSPS 120 = 250 MSPS ...
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... AD9239 0 –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 10. Single-Tone 32k FFT with f = 171.3 MHz –20 –40 –60 –80 –100 –120 FREQUENCY (MHz) Figure 11. Single-Tone 32k FFT with f = 240.3 MHz 250MSPS ...
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... AIN1 AND AIN2 = –7.0dBFS SFDR = 74.29dBc IMD2 = –76.51dBc –20 IMD3 = –74.30dBc –40 –60 –80 –100 –120 FREQUENCY (MHz) = 170.2 MHz and f IN1 f = 250 MSPS SAMPLE AD9239 80 100 = 171.3 MHz, IN2 100 120 = 141.3 MHz, IN2 100 120 = 171.3 MHz, IN2 ...
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... AD9239 SFDR (dB SNR (dB 100 150 200 250 300 AIN FREQUENCY (MHz) Figure 22. SNR/SFDR Amplitude vs. AIN Frequency SFDR (dB SNR (dB 100 150 200 250 300 AIN FREQUENCY (MHz) Figure 23. SNR/SFDR Amplitude vs. AIN Frequency, f ...
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... MORE 1.0 = 210 MSPS Figure 33. SNR/SFDR vs. Analog Input Common-Mode Voltage, Rev Page AD9239 INPUT REFERRED NOISE: 0.71 LSB N – – MORE BIN = 250 MSPS SAMPLE NPR = 52dB NOTCH = 18.9MHz NOTCH WIDTH = 1MHz ...
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... AD9239 0 –1 –2 –3 –4 –5 –6 –7 –8 –9 –10 1M 10M 100M AIN FREQUENCY (Hz) Figure 34. Full-Power Bandwidth Amplitude vs. AIN Frequency, f –3dB CUTOFF = 780MHz 1G 10G = 250 MSPS SAMPLE Rev Page ...
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... Rev Page AVDD AVDD 250Ω SDI/SDIO 30kΩ Figure 39. Equivalent SDI/SDIO Input Circuit AVDD TEMPOUT Figure 40. Equivalent TEMPOUT Output Circuit 100Ω 175Ω RBIAS Figure 41. Equivalent RBIAS Input/Output Circuit 175Ω VCMx Figure 42. Equivalent VCMx Output Circuit AD9239 ...
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... AD9239 DRVDD 4mA R TERM V DOUT + x CM 4mA Figure 43. Equivalent Digital Output Circuit 4mA DOUT – x 4mA Rev Page AVDD SDO AVDD 345Ω Figure 44. Equivalent SDO Output Circuit ...
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... Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9239, the default input span is 1.25 V p-p. To configure the ADC for a different input span, see Register 18. For the best performance, an input span of 1.25 V p-p or greater should be used (see Table 15 for details) ...
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... For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 47 to Figure 49), to achieve the true performance of the AD9239. Regardless of the configuration, the value of the shunt capacitor dependent on the input frequency and may need to be reduced or removed ...
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... This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally to 1.2 V and require no additional biasing. Figure 52 shows a preferred method for clocking the AD9239. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-to- back Schottky diodes across the secondary transformer limit clock excursions into the AD9239 to approximately 0 ...
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... Figure 57). The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9239. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise ...
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... Digital Start-Up Sequence The output digital data from the AD9239 is coded and packetized, which requires the device to have a certain start-up sequence. The following steps should be initialized by the user to capture coherent data at the receiving logic. 1. Initialize a soft reset via Bit 5 of Register 0 (see Table 15). ...
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... AD9239 HEIGHT1: EYE DIAGRAM (y1) –375.023m 600 (y2) +409.847m (Δy) +784.671m 400 200 0 –200 –400 EYE: ALL BITS OFFSET: 0.015 –600 ULS: 5000: 40044, TOTAL: 12000: 80091 –200 –100 0 100 TIME (ps) Figure 63. Digital Outputs Data Eye with Trace Lengths Less than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver ...
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... Digital Output Scrambler and Error Code Correction The data from the AD9239 is sent serially in packets of 64 bits. These numbers are derived from the necessity to have the output data streaming at 16× the encode clock. The data packets consist of a header, data, and error correction code (that is, 8 Bits of Header + 48 Bits of Data (4 Conv ...
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... AD9239 Scramblers There are three scramblers on the AD9239. The scramblers are Ethernet scrambler ( 1), a SONET scrambler ( 1), and a static inverter scrambler (inverts bits at set locations in the packet). The scramblers are used to help balance the number of 1s and 0s in the packet. ...
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... Figure 67. Scrambler Inverters for 64-Bit Packet: 12-Bit Case Rev Page <10> <9> <8> <7> <6> <5> <4> <6> <5> <4> <3> <2> <1> <0> <2> <1> <0> <11> <10> <9> <8> AD9239 ...
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... AD9239 Calculating the Parity Bits for the Hamming Code The Hamming bits are defined as follows. The definition is shown in the charts for a 12-bit example. The Hamming parity bits are shown interleaved in the data. This makes it easier to see the numeric relationship. The decoding on the receive side ...
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... Figure 75. p6 Bit for 64-Bit Packet: 12-Bit Case Rev Page <11> <10> <9> <8> <7> <6> <5> <4> <4> <3> <2> <1> <2> <1> <0> <11> <10> <9> <8> <7> <6> <5> <4> <3> <2> <1> <0> <11> <10> <11> <10> <9> <8> <7> <6> <5> <7> <6> <5> <4> <3> <2> <1> AD9239 ...
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... PLL, and biasing networks. In this state, the ADC typically dissipates 3 mW. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset. The AD9239 returns to normal operating mode when the PDWN pin is pulled low. This pin is only 1.8 V tolerant. ...
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... If multiple SDI/SDIO pins share a common connection, care should be taken to ensure that proper V the same load for each AD9239, Figure 77 shows the number of SDI/SDIO pins that can be connected together and the resulting V level ...
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... AD9239 CSB SCLK DON’T CARE SDIO DON’T CARE R Table 14. Serial Timing Definitions Parameter Timing (Minimum, ns CLK EN_SDI/SDIO t 10 DIS_SDI/SDIO 1.800 1.795 1.790 1.785 1.780 1 ...
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... Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. DEFAULT VALUES When the AD9239 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 15, where an X refers to an undefined feature. ...
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... Bit 5 Bit 4 Bit 3 Bit 2 Soft 16 bit reset address (default mode for ADCs) 8-bit Chip ID Bits[2:0] 0x0B – AD9239 – 12-bit quad Speed grade 010 = 170 100 = 210 101 = 250 ADC A ADC B External PDWN pin function 00 = full PDWN (default standby ...
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... B12 B11 B10 B13 B12 B11 B10 B13 B12 B11 B10 Rev Page AD9239 Default Default (LSB) Value Notes/ Bit 1 Bit 0 (Hex) Comments VCM 0x00 enable off (default) 0x00 Device offset trim. Data format select ...
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... AD9239 Addr. Register (MSB) (Hex) Name Bit 7 Bit 6 1F user_ B7 B6 patt4_lsb (local) 20 user_ B15 B14 patt4_msb (local) 21 serial_control (global) 24 misr_lsb B7 B6 (local) 25 misr_msb B15 B14 (local) 32 adi_link_ Hamming options enable (global (default off 34 Channel ID (local) 50 coarse_ Gain adjust gain_adj ...
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... ADC is connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9239. An exposed continuous copper plane on the PCB should mate to the AD9239 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB ...
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... PIN 1 INDICATOR TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9239BCPZ-170 –40°C to +85°C AD9239BCPZ-210 –40°C to +85°C AD9239BCPZ-250 –40°C to +85°C AD9239-250KITZ RoHS Compliant Part. 0.60 0.42 0.24 54 0.50 9.75 BSC BSC SQ 0.50 37 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM COPLANARITY ...
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... NOTES Rev Page AD9239 ...
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... AD9239 NOTES ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06980-0-5/10(B) Rev Page ...