AD9239 Analog Devices, AD9239 Datasheet - Page 24

• Manufacturer Part Number: AD9239
• Description: Quad, 12-Bit, 170 MSPS/210 MSPS/250 MSPS Serial Output 1.8 V ADC
• Manufacturer: Analog Devices

Specifications of AD9239

• Resolution (bits): 12bit
• # Chan: 4
• Sample Rate: 250MSPS
• Interface: Ser
• Analog Input Type: Diff-Uni,SE-Uni
• Ain Range: 1.25 V p-p
• Adc Architecture: Pipelined
• Pkg Type: CSP

AD9239
An example of the digital output (default) data eye and a time
interval error (TIE) jitter histogram with trace lengths less than
6 inches on standard FR-4 material is shown in Figure 63.
Figure 64 shows an example of trace lengths exceeding 12 inches
on standard FR-4 material. Notice that the TIE jitter histogram
reflects the decrease of the data eye opening as the edge deviates
from the ideal position. It is the user’s responsibility to determine
if the waveforms meet the timing budget of the design when the
trace lengths exceed 6 inches.
Additional SPI options allow the user to further increase the
output driver voltage swing of all four outputs in order to drive
longer trace lengths (see Register 15 in Table 15). Even though
this produces sharper rise and fall times on the data edges and is
less prone to bit errors, the power dissipation of the DRVDD
supply increases when this option is used. See the Memory Map
section for more details.
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 9.
–200
–400
–600
–200
–400
–600
600
400
200
600
400
200
Figure 64. Digital Outputs Data Eye with Trace Lengths Greater than 12 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
0
0
Figure 63. Digital Outputs Data Eye with Trace Lengths Less than 6 Inches on Standard FR-4, External 100 Ω Terminations at Receiver
(y1)
(y2)
(Δy)
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL: 12000: 80091
–200
–200
(y1)
(y2)
(Δy)
EYE: ALL BITS
OFFSET: 0.015
ULS: 5000: 40044, TOTAL 8000: 40044
–375.023m
+409.847m
+784.671m
HEIGHT1: EYE DIAGRAM
HEIGHT1: EYE DIAGRAM
–402.016m
+398.373m
+800.389m
–100
–100
TIME (ps)
TIME (ps)
0
0
100
100
200
200
+
+
1
1
600
500
400
300
200
100
300
250
200
150
100
50
0
0
–30
–50
Rev. B | Page 24 of 40
TIE1: HISTOGRAM
TIE1: HISTOGRAM
–10
TIME (ps)
TIME (ps)
0
10
To change the output data format to twos complement or gray
code, see the Memory Map section.
Table 9. Digital Output Coding
Code
4095
2048
2047
0
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to N bits
times the sample clock rate, in addition to some amount of
overhead to account for the 8-bit header and error correction, for a
maximum of 3.15 Gbps (that is, 12 bits × 210 MSPS × 25% =
3.15 Gbps). The lowest typical clock rate is 100 MSPS. For clock
rates slower than 100 MSPS, refer to Register 21 in the SPI
Memory Map. This option allows the user to adjust the PLL
loop bandwidth in order to use clock rates as low as 50 MSPS.
30
50
(VIN + x) − (VIN − x),
Input Span = 1.25 V p-p (V)
+0.625
0.00
−0.000305
−0.625
2
+
2
+
0.0001
0.0001
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
0.01
0.01
–10
–12
–14
–10
–12
–14
–6
–8
–0.5
–6
–8
1
–0.5
1
TJ@BERI: BATHTUB
TJ@BERI: BATHTUB
ULS
ULS
0
0
Digital Output Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
0.5
0.5
+
3
3
+