AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 899

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

32.6.3.13
32.6.3.14
32.6.3.15
9166C–AVR-08/11
TXOUTI
FIFOCON
Alternate pipe
Data flow error
CRC error
• Multi packet mode for OUT pipes
SW
Figure 32-23. Example of an OUT pipe with two data banks and a bank switching delay
See section
OUT pipe.
The user has the possibility to run sequentially several logical pipes on the same physical pipe.
Before switching pipe, the user should save the pipe context (UPCFGn, UPCONn, UPSTAn,
and the pipe descriptor table).
After switching pipe, the user should restore the pipe context, current bank number, and the cur-
rent data toggle by using the UPCONn.INITDTGL and UPCONn.INITBK bits.
This error exists only for isochronous and interrupt pipes for both IN and OUT directions. It sets
the Errorflow Interrupt (ERRORFI) bit in UPSTAn, which triggers an PnINT interrupt if the Error-
f l o w I n t e r r u p t E n a b l e ( E R R O R F E ) b i t i s o n e . T h e u s e r c a n c h e c k t h e
Pn_CTR_STA_BK0/1.UNDERF and OVERF bits in the pipe descriptor to see which current
bank has been affected.
This error exists only for isochronous IN pipes. It sets the CRC Error Interrupt bit (CRCERRI),
which triggers a PnINT interrupt if the CRC Error Interrupt Enable bit (UPCONn.CRCERRE) is
one.
write data to CPU
• An overflow can occur during an OUT stage if the host attempts to send data from an empty
• An underflow can occur during an IN stage if the device tries to send a packet while the bank
bank. The pipe descriptor Pn_CTR_STA_BK0/1.OVERF points out the bank from which the
OUT data should have originated. If the UPSTAn.ERRORFI bit is cleared and a new
transaction is successful, the Pn_CTR_STA_BK0/1.OVERF bit will be cleared.
is full. Typically this occurs when a CPU is not fast enough. The packet data is not written to
the bank and is lost. The pipe descriptor Pn_CTR_STA_BK0/1.UNDERF points out which
bank the OUT data was destined to. If UPSTAn.UNDERFI is zero and a new successful
transaction occurs, Pn_CTR_STA_BK0/1.UNDERF will be cleared.
BANK 0
”Multi packet mode for IN endpoints” on page 886
SW
OUT
SW
write data to CPU
BANK 1
(bank 0)
DATA
SW
ACK
HW
SW
OUT
and just replace IN endpoints with
write data to CPU
BANK0
(bank 1)
DATA
AT32UC3C
ACK
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