AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 705

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

27.8.5.2
27.8.6
Figure 27-10. User Sends Data While the Bus is Busy
9166C–AVR-08/11
TWI DATA transfer
(DADR + W + START + Write THR)
Multi-master Mode
TWCK
TWD
Data Receive with the Peripheral DMA Controller
A transfer is programmed
More than one master may access the bus at the same time without data corruption by using
arbitration.
Arbitration starts as soon as two or more masters place information on the bus at the same time,
and stops (arbitration is lost) for the master that intends to send a logical one while the other
master sends a logical zero.
As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to
detect a STOP. The SR.ARBLST flag will be written to one. When the STOP is detected, the
master who lost arbitration may reinitiate the data transfer.
Arbitration is illustrated in
If the user starts a transfer and if the bus is busy, the TWIM automatically waits for a STOP con-
dition on the bus before initiating the transfer (see
Note:
3. Start the transfer by enabling the Peripheral DMA Controller to transmit.
4. Wait for the Peripheral DMA Controller end-of-transmit flag.
5. Disable the Peripheral DMA Controller.
1. Initialize the receive Peripheral DMA Controller (memory pointers, size, etc.).
2. Configure the TWIM (ADR, NBYTES, etc.).
3. Start the transfer by enabling the Peripheral DMA Controller to receive.
4. Wait for the Peripheral DMA Controller end-of-receive flag.
5. Disable the Peripheral DMA Controller.
The state of the bus (busy or free) is not indicated in the user interface.
DATA sent by a master
Bus is busy
STOP sent by the master
Transfer is kept
Figure
27-11.
Bus is free
Bus is considered as free
Transfer is initiated
Figure
START sent by the TWI
27-10).
DATA sent by the TWI
AT32UC3C
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