AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 83

• Manufacturer Part Number: AT32UC3C2512C Automotive
• Manufacturer: Atmel Corporation

8.5.3.1
8.5.4
9166C–AVR-08/11
Osc0 clock
Osc1 clock
Generic Clocks
Enabling the PLL
PLLOSC
0
1
Figure 8-2.
PLLn is enabled by writing a one to the PLLEN bit in the PLLn register. PLLOSC selects Oscilla-
tor 0 or 1 as clock source. The PLLMUL and PLLDIV bit fields must be written with the
multiplication and division factors.
The PLLn.PLLOPT field should be set to proper values according to the PLL operating fre-
quency. The PLLOPT field can also be set to divide the output frequency of the PLLs by 2.
The lock signal for each PLL is available as a LOCKn flag in POSCSR. An interrupt can be gen-
erated on a 0 to 1 transition of these bits.
Timers, communication modules, and other modules connected to external circuitry may require
specific clock frequencies to operate correctly. The SCIF contains an implementation defined
number of generic clocks that can provide a wide range of accurate clock frequencies.
Each generic clock module runs from either clock source listed in
page
clock can be independently enabled and disabled, and is also automatically disabled along with
peripheral clocks by the Sleep Controller in the Power Manager.
117. The selected source can optionally be divided by any even integer up to 512. Each
Divider
PLLDIV
Input
PLL with control logic and filters
f
IN
Divider
Output
PLLMUL
PLLOPT
PLLEN
PLL
Mask
”Generic Clock Source” on
LOCK
AT32UC3C
PLL clock
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