AT32UC3C2512C Automotive Atmel Corporation, AT32UC3C2512C Automotive Datasheet - Page 252
AT32UC3C2512C Automotive
Manufacturer Part Number
AT32UC3C2512C Automotive
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT90CAN128_AUTOMOTIVE.pdf
(225 pages)
2.AT32UC3C0512C_AUTOMOTIVE.pdf
(1312 pages)
3.AT32UC3C0512C_AUTOMOTIVE.pdf
(107 pages)
- AT90CAN128_AUTOMOTIVE PDF datasheet
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #2
- AT32UC3C0512C_AUTOMOTIVE PDF datasheet #3
- Current page: 252 of 1312
- Download datasheet (20Mb)
15. Flash Controller (FLASHC)
15.1
15.2
15.3
15.3.1
15.3.2
15.3.3
9166C–AVR-08/11
Features
Overview
Product Dependencies
Power Management
Clocks
Interrupt
Rev: 3.0.2.2
•
•
•
•
•
•
•
•
•
•
•
•
•
The Flash Controller (FLASHC) interfaces the on-chip flash memory with the 32-bit internal HSB
bus. The controller manages the reading, writing, erasing, locking, and unlocking sequences.
In order to use this module, other parts of the system must be configured correctly, as described
below.
If the CPU enters a sleep mode that disables clocks used by the FLASHC, the FLASHC will stop
functioning and resume operation after the system wakes up from sleep mode.
The FLASHC has two bus clocks connected: One High Speed Bus clock (CLK_FLASHC_HSB)
and one Peripheral Bus clock (CLK_FLASHC_PB). These clocks are generated by the Power
Manager. Both clocks are enabled at reset, and can be disabled by writing to the Power Man-
ager. The user has to ensure that CLK_FLASHC_HSB is not turned off before reading the flash
or writing the pagebuffer and that CLK_FLASHC_PB is not turned off before accessing the
FLASHC configuration and control registers. Failing to do so may deadlock the bus.
The FLASHC interrupt request lines are connected to the interrupt controller. Using the FLASHC
interrupts requires the interrupt controller to be programmed first.
Controls flash block with dual read ports allowing staggered reads.
Supports 0 and 1 wait state bus access.
Allows interleaved burst reads for systems with one wait state, outputting one 32-bit word per
clock cycle.
32-bit HSB interface for reads from flash array and writes to page buffer.
32-bit PB interface for issuing commands to and configuration of the controller.
16 lock bits, each protecting a region consisting of (total number of pages in the flash block / 16)
pages.
Regions can be individually protected or unprotected.
Additional protection of the Boot Loader pages.
Supports reads and writes of general-purpose NVM bits.
Supports reads and writes of additional NVM pages.
Supports device protection through a security bit.
Dedicated command for chip-erase, first erasing all on-chip volatile memories before erasing
flash and clearing security bit.
AT32UC3C
252
Related parts for AT32UC3C2512C Automotive
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
Atmel Corporation
Datasheet:
Part Number:
Description:
INTERVAL AND WIPE/WASH WIPER CONTROL IC WITH DELAY
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Low-Voltage Voice-Switched IC for Hands-Free Operation
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
MONOLITHIC INTEGRATED FEATUREPHONE CIRCUIT
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
AM-FM Receiver IC U4255BM-M
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Monolithic Integrated Feature Phone Circuit
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Multistandard Video-IF and Quasi Parallel Sound Processing
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
High-performance EE PLD
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Flash Microcontroller
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
2-Wire Serial EEPROM
Manufacturer:
ATMEL Corporation
Datasheet: