ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 76

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

6.8
6.8.1
8331A–AVR–07/11
Register Description
CHnMUX – Event Channel n Multiplexer Register
The angle of a quadrature encoder attached to QDPH0, QDPH90 (and QINDX) can now be read
directly from the timer/counter count register. If the count register is different from BOTTOM
when the index is recognized, the timer/counter error flag is set. Similarly, the error flag is set if
the position counter passes BOTTOM without the recognition of the index.
• Bit 7:0 – CHnMUX[7:0]: Channel Multiplexer
These bits select the event source according to
devices regardless of whether the peripheral is present or not. Selecting event sources from
peripherals that are not present will give the same result as when this register is zero. When this
register is zero, no events are routed through. Manually generated events will override CHnMUX
and be routed to the event channel even if this register is zero.
Table 6-3.
Bit
Read/Write
Initial Value
• Set the period register of the timer/counter to ('line count' * 4 - 1), the line count of the
• Enable the timer/counter without clock prescaling.
CHnMUX[7:4]
quadrature encoder.
0000
0000
0000
0000
0000
0000
0000
0000
0000
0001
0001
0001
0001
R/W
CHnMUX[7:0] bit settings.
7
0
CHnMUX[3:0]
0
0
0
0
1
1
1
1
1
0
0
0
0
R/W
0
0
0
1
0
0
0
0
1
0
0
0
0
6
0
X
X
0
0
1
0
0
1
1
0
0
1
1
X
X
X
X
R/W
0
1
0
1
0
0
1
0
1
5
0
Group Configuration
RTC_OVF
RTC_CMP
ACA_CH0
ACA_CH1
ACA_WIN
ACB_CH0
R/W
4
0
CHnMUX[7:0]
Table
Atmel AVR XMEGA AU
R/W
3
0
6-3. This table is valid for all XMEGA
R/W
Event Source
None (manually generated events
only)
(Reserved)
(Reserved)
(Reserved)
RTC overflow
RTC compare match
USB start of frame on CH0
USB error on CH1
USB overflow on CH2
USB setup on CH3
(Reserved)
(Reserved)
ACA channel 0
ACA channel 1
ACA window
ACB channel 0
2
0
R/W
1
0
(2)
(2)
R/W
0
0
(2)
(2)
CHnMUX
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