ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 196

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

15.10.3
15.10.4
15.10.5
8331A–AVR–07/11
CTRLC — Control Register C
CTRLE — Control Register E
INTCTRLA — Interrupt Enable Register A
• Bit 7:0 – CMPHx/CMPLx: Compare Output Value High/Low x
These bits allow direct access to the Waveform Generator's output compare value when the
Timer/Counter is OFF. This is used to set or clear the WG output value when the Timer/Counter
is not running.
• Bit 7:2 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 0:1 – BYTEM[1:0]: Byte Mode
These bits select the Timer/Counter operation mode according to
Table 15-3.
• Bit 7:4 – Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
Bit
+0x02
Read/Write
Initial Value
CMD
00
01
10
11
CMPHD
R/W
7
–
R
0
Clock Select
7
0
R
7
–
0
NORMAL
BYTEMODE
SPLITMODE
Group Configuration
CMPHC
R/W
R
6
–
0
6
0
R
6
–
0
CMPHB
R/W
R
5
–
0
R
5
0
5
–
0
Description
Timer/Counter is set to Normal Mode (Timer/Counter type 0)
Upper byte of the counter (CNTH) will be set to zero after
each counter clock.
Timer/Counter is split into two 8-bit Timer/Counters
(Timer/Counter type 2)
Reserved
CMPHA
R/W
R
4
0
4
–
0
R
4
–
0
CMPLD
Atmel AVR XMEGA AU
R/W
R/W
UNFHINTLVL[1:0]
3
–
R
0
3
0
3
0
CMPLC
R/W
R/W
R
2
0
2
–
0
2
0
Table 15-3 on page
CMPLB
R/W
R/W
R/W
UNFLINTLVL[1:0]
1
0
1
0
1
0
BYTEM[1:0]
CMPLA
R/W
R/W
R/W
0
0
0
0
0
0
196.
INTCTRLA
CTRLC
CTRLE
196