ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 14

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

3.14
3.14.1
3.14.2
3.14.3
8331A–AVR–07/11
Register Descriptions
CCP – Configuration Change Protection Register
RAMPD – Extended Direct Addressing Register
RAMPX – Extended X-Pointer Register
• Bit 7:0 – CCP[7:0]: Configuration Change Protection
The CCP register must be written with the correct signature to enable change of the protected
I/O register or execution of the protected instruction for a maximum period of four CPU instruc-
tion cycles. All interrupts are ignored during these cycles. After these cycles, interrupts will
automatically be handled again by the CPU, and any pending interrupts will be executed accord-
ing to their level and priority. When the protected I/O register signature is written, CCP[0] will
read as one as long as the protected feature is enabled. Similarly when the protected SPM/LPM
signature is written, CCP[1] will read as one as long as the protected feature is enabled.
CCP[7:2] will always read as zero.
modes.
Table 3-1.
This register is concatenated with the operand for direct addressing (LDS/STS) of the whole
data memory space on devices with more than 64KB of data memory. This register is not avail-
able if the data memory, including external memory, is less than 64KB.
• Bit 7:0 – RAMPD[7:0]: Extended Direct Addressing bits
These bits hold the MSB of the 24-bit address created by RAMPD and the 16-bit operand. Only
the number of bits required to address the available data memory is implemented for each
device. Unused bits will always read as zero.
This register is concatenated with the X-register for indirect addressing (LD/LDD/ST/STD) of the
whole data memory space on devices with more than 64KB of data memory. This register is not
available if the data memory, including external memory, is less than 64KB.
Bit
+0x04
Read/Write
Initial Value
Bit
+0x08
Read/Write
Initial Value
Signature
0x9D
0xD8
R/W
W
7
0
7
0
Modes of CPU change protection.
R/W
W
6
0
6
0
Group Configuration
R/W
W
5
0
5
0
IOREG
SPM
Table 3-1 on page 14
R/W
W
4
0
4
0
RAMPD[7:0]
CCP[7:0]
Description
Protected SPM/LPM
Protected IO register
R/W
Atmel AVR XMEGA AU
W
3
0
3
0
shows the signature for the various
R/W
W
2
0
2
0
R/W
R/W
1
0
1
0
R/W
R/W
0
0
0
0
RAMPD
CCP
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