ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 157

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ATxmega64A3U

Manufacturer Part Number
ATxmega64A3U
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATxmega64A3U

Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes

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13.14.5
8331A–AVR–07/11
EBIOUT – EBI Output Register
Table 13-7 on page 157
Table 13-7.
• Bits 3:2 – CLKOUTSEL[1:0] : Clock Output Select
These bits are used to select which of the peripheral clocks will be output to the port pin if CLK-
OUT is configured.
Table 13-8.
• Bit 1:0 – CLKOUT[1:0]: Clock Output Port
These bits decide which port the peripheral clock will be output to. Pin 7 on the selected port is
the default used. The CLKOUT setting will override the EVOUT setting. Thus, if both are
enabled on the same port pin, the peripheral clock will be visible. The port pin must be config-
ured as output for the clock to be available on the pin.
Table 13-9 on page 157
Table 13-9.
• Bit 7:4 – Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
Bit
+0x05
Read/Write
Initial Value
CLKOUT[1:0]
00
01
10
11
CLKOUTSEL[1:0]
EVOUT[1:0]
00
01
10
11
00
01
10
R
7
0
Event output pin selection.
Event output clock selection.
Clock output port configurations.
R
6
0
shows the possible configurations.
shows the possible configurations.
Group Configuration
OFF
PC
PD
PE
Group Configuration
Group Configuration
CLK1X
CLK2X
CLK4X
R
5
0
OFF
PC
PD
PE
R
4
0
Description
Event output disabled
Event channel 0 output on PORTC
Event channel 0 output on PORTD
Event channel 0 output on PORTE
Description
CLK
CLK
CLK
Description
Clock output disabled
Clock output on PORTC
Clock output on PORTD
Clock output on PORTE
Atmel AVR XMEGA AU
R/W
EBIADROUT[1:0]
3
0
PER
PER2
PER4
output to pin
output to pin
output to pin
R/W
2
0
R/W
1
EBICSOUT[1:0]
0
R/W
0
0
CLKEVOUT
157

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