ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 499

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

8331A–AVR–07/11
20 USB – Universal Serial Bus Interface ................................................. 231
21 TWI – Two-Wire Interface .................................................................... 259
19.4
19.5
20.1
20.2
20.3
20.4
20.5
20.6
20.7
20.8
20.9
20.10
20.11
20.12
20.13
20.14
20.15
20.16
20.17
20.18
20.19
21.1
21.2
21.3
21.4
21.5
21.6
21.7
21.8
21.9
21.10
21.11
21.12
Register Summary .........................................................................................230
Interrupt Vector Summary .............................................................................230
Features ........................................................................................................231
Overview ........................................................................................................231
Operation .......................................................................................................233
SRAM Memory Mapping ...............................................................................237
Clock Generation ...........................................................................................238
Ping-Pong Operation .....................................................................................239
Multi-packet transfers ....................................................................................240
Auto Zero Length Packet ...............................................................................241
Transaction Complete FIFO ..........................................................................241
Interrupts and Events ....................................................................................242
VBUS Detection .............................................................................................244
On-Chip Debug ..............................................................................................244
Register Description – USB ...........................................................................245
Register Description – USB Endpoint ............................................................252
Register Description - Frame .........................................................................257
Register Summary – USB Module .................................................................258
Register Summary – USB Endpoint ..............................................................258
Register Summary – Frame ..........................................................................258
USB Interrupt Vector Summary .....................................................................258
Features ........................................................................................................259
Overview ........................................................................................................259
General TWI Bus Concepts ...........................................................................260
TWI Bus State Logic ......................................................................................265
TWI Master Operation ...................................................................................266
TWI Slave Operation .....................................................................................268
Enabling External Driver Interface .................................................................270
Register Description - TWI ............................................................................271
Register Description – TWI Master ................................................................272
Register Description – TWI Slave ..................................................................277
Register Summary - TWI ...............................................................................283
Register Summary - TWI Master ...................................................................283
Atmel AVR XMEGA AU
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