ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 321

• Manufacturer Part Number: ATxmega64A3U
• Manufacturer: Atmel Corporation

Specifications of ATxmega64A3U

• Flash (kbytes): 64 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 32 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 50
• Ext Interrupts: 50
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 10
• Twi (i2c): 2
• Uart: 7
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 16
• Adc Resolution (bits): 12
• Adc Speed (ksps): 2000
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 12
• Temp. Sensor: Yes
• Crypto Engine: AES/DES
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 1.6 to 3.6
• Operating Voltage (vcc): 1.6 to 3.6
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 7
• Output Compare Channels: 22
• Input Capture Channels: 22
• Pwm Channels: 22
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

25.5.2
25.5.3
8331A–AVR–07/11
STATUS
STATE
–
–
AES State Register
AES Status Register
• Bit 1:0
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 7
The ERROR flag indicates an illegal handling of the AES crypto module. The flag is set in the fol-
lowing cases:
This flag can be cleared by software by writing one to its bit location.
• Bit 6:1
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
• Bit 0
This flag is the interrupt/DMA request flag, and is set when the encryption/decryption procedure
is completed and the state memory contains valid data. As long as the flag is zero, this indicates
that there is no valid encrypted/decrypted data in the state memory.
The flag is cleared by hardware when a read access is made to the state memory (the first byte
is read). Alternatively, the bit can be cleared by writing a one to its bit location.
The STATE register is used to access the state memory. Before encryption/decryption can take
place, the state memory must be written sequentially, byte-by-byte, through the STATE register.
After encryption/decryption is done, the ciphertext/plaintext can be read sequentially, byte-by-
byte, through the STATE register.
Loading the initial data to the STATE register should be done after setting the appropriate AES
mode and direction. This register can not be accessed during encryption/decryption.
• Setting START in the control register while the state memory and/or key memory are not fully
• Accessing (read or write) the control register while the START bit is one.
Bit
+0x01
Read/Write
Initial Value
loaded or read. This error occurs when the total number of read/write operations from/to the
STATE and KEY registers is not a multiple of 16 before an AES start.
Bit
+0x02
Read/Write
Initial Value
–
–
–
–
ERROR: Error
SRIF: State Ready Interrupt flag
Reserved
Reserved
ERROR
R/W
7
0
R/W
7
0
R
6
–
0
R/W
6
0
R
5
–
0
R/W
5
0
R
4
–
0
R/W
4
0
STATE[7:0]
Atmel AVR XMEGA AU
R
R/W
3
–
0
3
0
R/W
R
2
–
0
2
0
R/W
R
1
–
0
1
0
SRIF
R/W
R/W
0
0
0
0
STATUS
STATE
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