ATxmega64A3U Atmel Corporation, ATxmega64A3U Datasheet - Page 286
ATxmega64A3U
Manufacturer Part Number
ATxmega64A3U
Description
Manufacturer
Atmel Corporation
Specifications of ATxmega64A3U
Flash (kbytes)
64 Kbytes
Pin Count
64
Max. Operating Frequency
32 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
50
Ext Interrupts
50
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device
Spi
10
Twi (i2c)
2
Uart
7
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
16
Adc Resolution (bits)
12
Adc Speed (ksps)
2000
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
12
Temp. Sensor
Yes
Crypto Engine
AES/DES
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
1.6 to 3.6
Operating Voltage (vcc)
1.6 to 3.6
Fpu
No
Mpu / Mmu
no / no
Timers
7
Output Compare Channels
22
Input Capture Channels
22
Pwm Channels
22
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATxmega64A3U-AU
Manufacturer:
ACTEL
Quantity:
101
Part Number:
ATxmega64A3U-MH
Manufacturer:
TI/德州仪器
Quantity:
20 000
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22.5
22.6
8331A–AVR–07/11
Data Modes
DMA Support
There are four combinations of SCK phase and polarity with respect to serial data. The SPI data
transfer formats are shown in
edges of the SCK signal, ensuring sufficient time for data signals to stabilize.
The leading edge is the first clock edge of a clock cycle. The trailing edge is the last clock edge
of a clock cycle.
Figure 22-2. SPI transfer modes.
DMA support on the SPI module is available only in slave mode. The SPI slave can trigger a
DMA transfer as one byte has been shifted into the DATA register. It is possible, however, to use
the XMEGA USART in SPI mode and then have DMA support in master mode. For details, refer
to
”USART in Master SPI Mode” on page
Mode 0
Mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
Mode 1
Mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Figure
MSB
LSB
Bit 6
Bit 1
22-2. Data bits are shifted out and latched in on opposite
Bit 6
Bit 1
302.
Bit 5
Bit 2
Bit 5
Bit 2
Bit 4
Bit 3
Atmel AVR XMEGA AU
Bit 4
Bit 3
Bit 3
Bit 4
Bit 3
Bit 4
Bit 2
Bit 5
Bit 2
Bit 5
Bit 1
Bit 6
Bit 1
Bit 6
LSB
MSB
LSB
MSB
286
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