ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 85

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

12.7.3
8048B–AVR–03/09
Fast PWM Mode
The timing diagram for the CTC mode is shown in
(TCNTn) increases until a Compare Match occurs between TCNTn and OCRnA, and then coun-
ter (TCNTn) is cleared.
Figure 12-5. CTC Mode, Timing Diagram
An interrupt can be generated each time the counter value reaches the TOP value by using the
OCFnA Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating
the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-
ning with none or a low prescaler value must be done with care since the CTC mode does not
have the double buffering feature. If the new value written to OCRnA is lower than the current
value of TCNTn, the counter will miss the Compare Match. The counter will then have to count to
its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can
occur.
For generating a waveform output in CTC mode, the OCnA output can be set to toggle its logical
level on each Compare Match by setting the Compare Output mode bits to toggle mode
(COMnA1:0 = 1). The OCnA value will not be visible on the port pin unless the data direction for
the pin is set to output. The waveform generated will have a maximum frequency of f
f
equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOVn Flag is set in the same timer clock cycle that the
counter counts from MAX to 0x00.
The fast Pulse Width Modulation or fast PWM mode (WGMn2:0 = 3 or 7) provides a high fre-
quency PWM waveform generation option. The fast PWM differs from the other PWM option by
its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-
TOM. TOP is defined as 0xFF when WGMn2:0 = 3, and OCRnA when WGMn2:0 = 7. In non-
inverting Compare Output mode, the Output Compare (OCnx) is cleared on the Compare Match
between TCNTn and OCRnx, and set at BOTTOM. In inverting Compare Output mode, the out-
put is set on Compare Match and cleared at BOTTOM. Due to the single-slope operation, the
operating frequency of the fast PWM mode can be twice as high as the phase correct PWM
mode that use dual-slope operation. This high frequency makes the fast PWM mode well suited
clk_I/O
TCNTn
OCn
(Toggle)
Period
/2 when OCRnA is set to zero (0x00). The waveform frequency is defined by the following
1
f
2
OCnx
=
------------------------------------------------- -
2 N
3
⋅
⋅
f
(
clk_I/O
1
+
Figure 12-5 on page
4
OCRnx
)
85. The counter value
OCnx Interrupt Flag Set
(COMnx1:0 = 1)
OCnx
85
=