ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 118
ATtiny43U
Manufacturer Part Number
ATtiny43U
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny43U
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
0.7 to 5.5
Operating Voltage (vcc)
0.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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ATtiny43U
Figure 16-3. ADC Prescaler
When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion
starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles, as summarised in
first conversion after the ADC is switched on (ADEN in ADCSRA is set) takes 25 ADC clock
cycles in order to initialize the analog circuitry, as shown in
Figure 16-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-
sion and 13.5 ADC clock cycles after the start of a first conversion. See
conversion is complete, the result is written to the ADC Data Registers, and ADIF is set. In Sin-
gle Conversion mode, ADSC is cleared simultaneously. The software may then set ADSC again,
and a new conversion will be initiated on the first rising ADC clock edge.
Cycle Number
ADC Clock
ADEN
ADSC
ADIF
ADCH
ADCL
1
2
MUX and REFS
Update
ADEN
START
12
ADPS0
ADPS1
ADPS2
13
CK
14
15
Sample & Hold
16
Reset
First Conversion
17
18
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
19
20
21
Figure 16-4
22
Conversion
Complete
23
Table 16-1 on page
24
below.
25
Figure
Sign and MSB of Result
Next
Conversion
1
LSB of Result
16-5. When a
8048B–AVR–03/09
2
MUX and REFS
Update
120. The
3
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