ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 48
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ATtiny43U
Manufacturer Part Number
ATtiny43U
Description
Manufacturer
Atmel Corporation
Specifications of ATtiny43U
Flash (kbytes)
4 Kbytes
Pin Count
20
Max. Operating Frequency
8 MHz
Cpu
8-bit AVR
# Of Touch Channels
8
Hardware Qtouch Acquisition
No
Max I/o Pins
16
Ext Interrupts
16
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
4
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
0.25
Eeprom (bytes)
64
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
Yes
Temp. Range (deg C)
-40 to 85
I/o Supply Class
0.7 to 5.5
Operating Voltage (vcc)
0.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
4
Pwm Channels
4
32khz Rtc
No
Calibrated Rc Oscillator
Yes
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9. System Control and Reset
9.1
48
Resetting the AVR
ATtiny43U
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in
defines the electrical parameters of the reset circuitry.
Figure 9-1.
The I/O ports of the AVR are immediately reset to their initial state when a reset source goes
active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The time-out
period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-
ferent selections for the delay period are presented in
BODLEVEL [2..0]
Reset Logic
Pull-up Resistor
FILTER
SPIKE
CKSEL[1:0]
Power-on Reset
Reset Circuit
SUT[1:0]
Figure 9-1
Brown-out
Watchdog
Oscillator
Generator
Circuit
Clock
shows the reset logic.
CK
Register (MCUSR)
MCU Status
DATA BUS
“Clock Sources” on page
Delay Counters
Table 20-4 on page 158
TIMEOUT
24.
8048B–AVR–03/09
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