ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 100

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

14. USI – Universal Serial Interface
14.1
14.2
100
Features
Overview
ATtiny43U
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The Universal Serial Interface (USI), provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load.
A simplified block diagram of the USI is shown in
of I/O pins, refer to
bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed
in the
Figure 14-1. Universal Serial Interface, Block Diagram
The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly
accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register
(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register
must be read as quickly as possible to ensure that no data is lost.
The most significant bit of the USI Data Register is connected to one of two output pins (depend-
ing on the mode configuration, see
between the output of the USI Data Register and the output pin, which delays the change of data
Two-wire Synchronous Data Transfer (Master or Slave)
Three-wire Synchronous Data Transfer (Master or Slave)
Data Received Interrupt
Wakeup from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“Register Descriptions” on page
USIDR
USIDB
USISR
USICR
2
“Pinout of ATtiny43U” on page
4-bit Counter
Table 14-1 on page
107.
3
2
1
0
3
2
1
0
D Q
LE
[1]
Figure 14-1 on page
2. CPU accessible I/O Registers, including I/O
TIM0 COMP
0
1
108). There is a transparent latch
Two-wire Clock
Control Unit
100. For actual placement
CLOCK
HOLD
DO
DI/SDA
USCK/SCL
8048B–AVR–03/09
(Output only)
(Input/Open Drain)
(Input/Open Drain)