ATtiny43U Atmel Corporation, ATtiny43U Datasheet - Page 105

• Manufacturer Part Number: ATtiny43U
• Manufacturer: Atmel Corporation

Specifications of ATtiny43U

• Flash (kbytes): 4 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 8 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 8
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 16
• Ext Interrupts: 16
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 4
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 64
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: Yes
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 0.7 to 5.5
• Operating Voltage (vcc): 0.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 4
• Pwm Channels: 4
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

8048B–AVR–03/09
Figure 14-4. Two-wire Mode Operation, Simplified Diagram
The data direction is not given by the physical layer. A protocol, like the one used by the TWI-
bus, must be implemented to control the data flow.
Figure 14-5. Two-wire Mode, Typical Timing Diagram
Referring to the timing diagram
1. The start condition is generated by the master by forcing the SDA low line while keep-
SDA
SCL
SLAVE
MASTER
ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the
USI Data Register, or by setting the corresponding bit in the PORTA register to zero.
Note that the Data Direction Register bit must be set to one for the output to be
enabled. The start detector logic of the slave device (see
Bit7
Bit7
Bit6
Bit6
S
A B
Bit5
Bit5
C
ADDRESS
Bit4
Bit4
1 - 7
Bit3
Bit3
R/W
Bit2
Bit2
(Figure
8
D
Bit1
Bit1
14-5), a bus transfer involves the following steps:
ACK
9
Bit0
Bit0
E
DATA
1 - 8
Two-wire Clock
ACK
Control Unit
9
Figure 14-6 on page
PORTxn
DATA
1 - 8
HOLD
SCL
SDA
SCL
SDA
SCL
ACK
9
106)
F
P
VCC
105