ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 61

no-image

ATmega64M1

Manufacturer Part Number
ATmega64M1
Description
Manufacturer
Atmel Corporation
Datasheets

Specifications of ATmega64M1

Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATmega64M1-15AZ
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATmega64M1-15MD
Manufacturer:
ATMEL
Quantity:
700
Part Number:
ATmega64M1-AU
Manufacturer:
Atmel
Quantity:
10 000
12.2.3
12.2.4
8209D–AVR–11/10
EIFR – External Interrupt Flag Register
PCICR – Pin Change Interrupt Control Register
• Bit 7:4 – Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3:0 – INTF[3:0]: External Interrupt Flag 3:0
When an edge or logic change on the INT3:0 pin triggers an interrupt request, INTF3:0 becomes
set (one). If the I-bit in SREG and the corresponding interrupt enable bit INT3:0 in EIMSK, are
set (one), the MCU will jump to the interrupt vector. The flag is cleared when the interrupt routine
is executed. Alternatively, the flag can be cleared by writing a logical one to it. These flags are
always cleared when INT3:0 are configured as a level interrupt.
• Bit 7:4 - Res: Reserved
These bits are reserved and will always read as zero.
• Bit 3 - PCIE3: Pin Change Interrupt Enable 3
When the PCIE3 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 3 is enabled. Any change on any enabled PCINT26:24 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI3
Interrupt Vector. PCINT26:24 pins are enabled individually by the PCMSK3 Register.
• Bit 2 - PCIE2: Pin Change Interrupt Enable 2
When the PCIE2 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 2 is enabled. Any change on any enabled PCINT23:16 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI2
Interrupt Vector. PCINT23:16 pins are enabled individually by the PCMSK2 Register.
• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT14:8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT14:8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7:0 pin will cause an interrupt.
The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0 Inter-
rupt Vector. PCINT7:0 pins are enabled individually by the PCMSK0 Register.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
R
7
0
R
7
0
R
R
6
0
6
0
R
5
0
R
5
0
R
R
4
0
4
0
ATmega16M1/32M1/64M1
INTF3
PCIE3
R/W
3
0
R
3
0
INTF2
PCIE2
R/W
R/W
2
0
2
0
INTF1
PCIE1
R/W
R/W
1
0
1
0
INTF0
PCIE0
R/W
R/W
0
0
0
0
PCICR
EIFR
61

Related parts for ATmega64M1