ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 145
ATmega64M1
Manufacturer Part Number
ATmega64M1
Description
Manufacturer
Atmel Corporation
Specifications of ATmega64M1
Flash (kbytes)
64 Kbytes
Pin Count
32
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
12
Hardware Qtouch Acquisition
No
Max I/o Pins
27
Ext Interrupts
27
Usb Speed
No
Usb Interface
No
Spi
1
Uart
1
Can
1
Lin
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
11
Adc Resolution (bits)
10
Adc Speed (ksps)
125
Analog Comparators
4
Resistive Touch Screen
No
Dac Channels
1
Dac Resolution (bits)
10
Temp. Sensor
Yes
Crypto Engine
No
Sram (kbytes)
4
Eeprom (bytes)
2048
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
2
Output Compare Channels
14
Input Capture Channels
1
Pwm Channels
10
32khz Rtc
No
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATmega64M1-15MD
Manufacturer:
ATMEL
Quantity:
700
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17.12 Analog Synchronization
17.13 Interrupt Handling
17.14 PSC Clock Sources
8209D–AVR–11/10
Each PSC module generates a signal to synchronize the ADC sample and hold; synchronisation
is mandatory for measurements.
This signal can be selected between all falling or rising edge of PSCOUTnA or PSCOUTnB
outputs.
In center aligned mode, OCRnRAH/L is not used, so it can be used to specified the synchroniza-
tion of the ADC. It this case, it’s minimum value is 1.
As each PSC module can be dedicated for one function, each PSC has its own interrupt system.
List of interrupt sources:
Each PSC has two clock inputs:
Figure 17-15. Clock selection
PCLKSELn bit in PSC Control Register (PCTL) is used to select the clock source.
PPREn1/0 bits in PSC Control Register (PCTL) are used to select the divide factor of the clock.
Table 17-6.
PCLKSELn
0
0
0
• Counter reload (end of On Time 1)
• PSC Input event (active edge or at the beginning of level configured event)
• PSC Mutual Synchronization Error
• CLK PLL from the PLL
• CLK I/O
CLK
CLK
Output Clock versus Selection and Prescaler
PLL
I/O
PPREn1
0
0
1
PCLKSEL
1
0
PPREn0
0
1
0
CK
ATmega16M1/32M1/64M1
PRESCALER
CLKPSCn output
CLK I/O
CLK I/O / 4
CLK I/O / 32
CLK
PSCn
PPREn1/0
145
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