ATmega64M1 Atmel Corporation, ATmega64M1 Datasheet - Page 133

• Manufacturer Part Number: ATmega64M1
• Manufacturer: Atmel Corporation

Specifications of ATmega64M1

• Flash (kbytes): 64 Kbytes
• Pin Count: 32
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 12
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 27
• Ext Interrupts: 27
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Uart: 1
• Can: 1
• Lin: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 4
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 4
• Eeprom (bytes): 2048
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 2
• Output Compare Channels: 14
• Input Capture Channels: 1
• Pwm Channels: 10
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

17. PSC – Power Stage Controller
17.1
17.2
17.3
8209D–AVR–11/10
Features
Overview
Accessing 16-bit Registers
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The Power Stage Controller is a high performance waveform controller.
Many register and bit references in this section are written in general form.
The purpose of the Power Stage Controller (PSC) is to control an external power interface. It has
six outputs to drive for example a 3 half-bridge. This feature allows you to generate three phase
waveforms for applications such as Asynchronous or BLDC motor drives, lighting systems...
The PSC also has 3 inputs, the purpose of which is to provide fast emergency stop capability.
The PSC outputs are programmable as “active high” or “active low”. All the timing diagrams in
the following examples are given in the “active high” polarity.
Some PSC registers are 16-bit registers. These registers can be accessed by the AVR CPU via
the 8-bit data bus. The 16-bit registers must be byte accessed using two read or write opera-
tions. The PSC has a single 8-bit register for temporary storing of the high byte of the 16-bit
access. The same temporary register is shared between all PSC 16-bit registers. Accessing the
low byte triggers the 16-bit read or write operation. When the low byte of a 16-bit register is writ-
ten by the CPU, the high byte stored in the temporary register, and the low byte written are both
copied into the 16-bit register in the same clock cycle. When the low byte of a 16-bit register is
read by the CPU, the high byte of the 16-bit register is copied into the temporary register in the
same clock cycle as the low byte is read.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the low
byte must be read before the high byte.
• A lower case “n” replaces the PSC module number, in this case 0, 1 or 2. However, when
• A lower case “x” replaces the PSC part , in this case A or B. However, when using the register
PWM waveform generation function with 6 complementary programmable outputs (able to
control 3 half-bridges)
Programmable dead time control
PWM up to 12 bit resolution
PWM clock frequency up to 64 MHz (via PLL)
Programmable ADC trigger
Automatic Overlap protection
Failsafe emergency inputs - 3 (to force all outputs to high impedance or in inactive state - fuse
configurable)
Center aligned and edge aligned modes synchronization
using the register or bit defines in a program, the precise form must be used, that is,
POCR0SAH for accessing module 0 POCRnSAH register and so on
or bit defines in a program, the precise form must be used, that is, OCR0SAH for accessing
part A OCR0SxH register and so on
ATmega16M1/32M1/64M1
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