ATmega16U4 Atmel Corporation, ATmega16U4 Datasheet - Page 132

• Manufacturer Part Number: ATmega16U4
• Manufacturer: Atmel Corporation

Specifications of ATmega16U4

• Flash (kbytes): 16 Kbytes
• Pin Count: 44
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 14
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 26
• Ext Interrupts: 13
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device
• Spi: 2
• Twi (i2c): 1
• Uart: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 12
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 2.1
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 12
• Input Capture Channels: 2
• Pwm Channels: 8
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

Table 14-5.
Note:
14.10.3
14.10.4
7766F–AVR–11/10
Mode
13
14
15
1. The CTCn and PWMn1:0 bit definition names are obsolete. Use the
WGMn3
Timer/Counter1 Control Register B – TCCR1B
Timer/Counter3 Control Register B – TCCR3B
location of these bits are compatible with previous versions of the timer.
1
1
1
Waveform Generation Mode Bit Description (Continued)
WGMn2
(CTCn)
1
1
1
• Bit 7 – ICNCn: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the Noise Canceler is
activated, the input from the Input Capture Pin (ICPn) is filtered. The filter function requires four
successive equal valued samples of the ICPn pin for changing its output. The input capture is
therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICESn: Input Capture Edge Select
This bit selects which edge on the Input Capture Pin (ICPn) that is used to trigger a capture
event. When the ICESn bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICESn bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICESn setting, the counter value is copied into the
Input Capture Register (ICRn). The event will also set the Input Capture Flag (ICFn), and this
can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICRn is used as TOP value (see description of the WGMn3:0 bits located in the
TCCRnA and the TCCRnB Register), the ICPn is disconnected and consequently the input cap-
ture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must be
written to zero when TCCRnB is written.
• Bit 4:3 – WGMn3:2: Waveform Generation Mode
See TCCRnA Register description.
• Bit 2:0 – CSn2:0: Clock Select
The three clock select bits select the clock source to be used by the Timer/Counter, see
13-8
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(PWMn1)
WGMn1
and
0
1
1
Figure
R/W
7
ICNC1
R/W
0
7
ICNC3
0
(PWMn0)
WGMn0
13-9.
1
0
1
6
ICES1
R/W
0
6
ICES3
R/W
0
Timer/Counter Mode of Operation
(Reserved)
Fast PWM
Fast PWM
5
–
R
0
5
–
R
0
4
WGM13
R/W
0
4
WGM33
R/W
0
(1)
WGM
3
WGM12
R/W
0
3
WGM32
R/W
0
n2:0 definitions. However, the functionality and
2
CS32
R/W
0
2
CS12
R/W
0
1
CS31
R/W
0
TOP
–
ICRn
OCRnA
1
CS11
R/W
0
ATmega16/32U4
0
CS30
R/W
0
0
CS10
R/W
0
Update of
OCRn
–
TOP
TOP
x
TCCR3B
TCCR1B
at
TOVn Flag
Set on
–
TOP
TOP
Figure
132