ATmega1280R212 Atmel Corporation, ATmega1280R212 Datasheet - Page 52

• Manufacturer Part Number: ATmega1280R212
• Manufacturer: Atmel Corporation

Specifications of ATmega1280R212

• Flash (kbytes): 128 Kbytes
• Max. Operating Frequency: 16 MHz
• Max I/o Pins: 86
• Spi: 5
• Twi (i2c): 1
• Uart: 4
• Adc Channels: 16
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Crypto Engine: AES
• Sram (kbytes): 8
• Eeprom (bytes): 4096
• Operating Voltage (vcc): 1.8 to 3.6
• Timers: 6
• Frequency Band: 700/800/900MHz
• Max Data Rate (mb/s): 1
• Antenna Diversity: No
• External Pa Control: Yes
• Power Output (dbm): 10
• Receiver Sensitivity (dbm): -110
• Receive Current Consumption (ma): 9.0
• Transmit Current Consumption (ma): 18 at 5dBm
• Link Budget (dbm): 120

11. Power Management and Sleep Modes
11.1
Table 11-1.
Notes:
11.2
2549N–AVR–05/11
Extended Standby
Sleep Mode
Power-down
Power-save
Standby
ADCNRM
Sleep Modes
1. Only recommended with external crystal or resonator selected as clock source.
2. If Timer/Counter2 is running in asynchronous mode.
3. For INT7:4, only level interrupt.
Idle Mode
Idle
(1)
Active Clock Domains and Wake-up Sources in the Different Sleep Modes.
Active Clock Domains
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The AVR provides various sleep modes allowing the user to tailor the power consump-
tion to the application’s requirements.
F i g u r e 1 0 - 1 o n p a g e 4 0
ATmega640/1280/1281/2560/2561, and their distribution. The figure is helpful in selecting an
appropriate sleep mode.
sources.
To enter any of the sleep modes, the SE bit in
56
SM0 bits in the SMCR Register select which sleep mode will be activated by the SLEEP instruc-
tion. See
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File and
SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,
the MCU wakes up and executes from the Reset Vector.
When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,
stopping the CPU but allowing the SPI, USART, Analog Comparator, ADC, 2-wire Serial Inter-
face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep
mode basically halts clk
must be written to logic one and a SLEEP instruction must be executed. The SM2, SM1, and
X
Table 11-2 on page 56
X
X
X
X
X
X
(2)
CPU
Table 11-1
and clk
Oscillators
X
X
X
X
ATmega640/1280/1281/2560/2561
for a summary.
FLASH
p r e s e n t s t h e d i f f e r e n t c l o c k s y s t e m s i n t h e
X
X
X
X
(2)
(2)
(2)
(2)
shows the different sleep modes and their wake-up
, while allowing the other clocks to run.
X
X
X
X
X
X
(3)
(3)
(3)
(3)
(3)
“SMCR – Sleep Mode Control Register” on page
X
X
X
X
X
X
X
Wake-up Sources
X
X
X
(2)
X
X
X
X
X
X
X
X
X
X
X
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