ATmega1280R212 Atmel Corporation, ATmega1280R212 Datasheet - Page 119
ATmega1280R212
Manufacturer Part Number
ATmega1280R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1280R212
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
86
Spi
5
Twi (i2c)
1
Uart
4
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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16.2.2
16.3
16.4
2549N–AVR–05/11
Timer/Counter Clock Sources
Counter Unit
Definitions
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B).
set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare
interrupt request.
Many register and bit references in this section are written in general form. A lower case “n”
replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-
pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or
bit defines in a program, the precise form must be used, that is, TCNT0 for accessing
Timer/Counter0 counter value and so on.
The definitions in
Table 16-1.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
16-2
Figure 16-2. Counter Unit Block Diagram
BOTTOM
MAX
TOP
shows a block diagram of the counter and its surroundings.
See “Output Compare Unit” on page 120.
“Timer/Counter 0, 1, 3, 4, and 5 Prescaler” on page
Definitions
DATA BUS
The counter reaches the BOTTOM when it becomes 0x00.
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
The counter reaches the TOP when it becomes equal to the highest value in the
count sequence. The TOP value can be assigned to be the fixed value 0xFF
(MAX) or the value stored in the OCR0A Register. The assignment is depen-
dent on the mode of operation.
TCNTn
Table 16-1
are also used extensively throughout the document.
ATmega640/1280/1281/2560/2561
direction
count
clear
bottom
Control Logic
for details. The Compare Match event will also
top
TOVn
(Int.Req.)
clk
Tn
169.
Clock Select
( From Prescaler )
Detector
Edge
Tn
T0
).
Figure
119
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