ATmega1280R212 Atmel Corporation, ATmega1280R212 Datasheet - Page 214
ATmega1280R212
Manufacturer Part Number
ATmega1280R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1280R212
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
86
Spi
5
Twi (i2c)
1
Uart
4
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
- Current page: 214 of 448
- Download datasheet (8Mb)
22.5.4
22.5.5
22.6
22.6.1
2549N–AVR–05/11
Data Reception – The USART Receiver
Parity Generator
Disabling the Transmitter
Receiving Frames with 5 to 8 Data Bits
When the Data Register Empty Interrupt Enable (UDRIEn) bit in UCSRnB is written to one, the
USART Data Register Empty Interrupt will be executed as long as UDREn is set (provided that
global interrupts are enabled). UDREn is cleared by writing UDRn. When interrupt-driven data
transmission is used, the Data Register Empty interrupt routine must either write new data to
UDRn in order to clear UDREn or disable the Data Register Empty interrupt, otherwise a new
interrupt will occur once the interrupt routine terminates.
The Transmit Complete (TXCn) Flag bit is set one when the entire frame in the Transmit Shift
Register has been shifted out and there are no new data currently present in the transmit buffer.
The TXCn Flag bit is automatically cleared when a transmit complete interrupt is executed, or it
can be cleared by writing a one to its bit location. The TXCn Flag is useful in half-duplex commu-
nication interfaces (like the RS-485 standard), where a transmitting application must enter
receive mode and free the communication bus immediately after completing the transmission.
When the Transmit Compete Interrupt Enable (TXCIEn) bit in UCSRnB is set, the USART
Transmit Complete Interrupt will be executed when the TXCn Flag becomes set (provided that
global interrupts are enabled). When the transmit complete interrupt is used, the interrupt han-
dling routine does not have to clear the TXCn Flag, this is done automatically when the interrupt
is executed.
The Parity Generator calculates the parity bit for the serial frame data. When parity bit is enabled
(UPMn1 = 1), the transmitter control logic inserts the parity bit between the last data bit and the
first stop bit of the frame that is sent.
The disabling of the Transmitter (setting the TXEN to zero) will not become effective until ongo-
ing and pending transmissions are completed, that is, when the Transmit Shift Register and
Transmit Buffer Register do not contain data to be transmitted. When disabled, the Transmitter
will no longer override the TxDn pin.
The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the
UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxDn
pin is overridden by the USART and given the function as the Receiver’s serial input. The baud
rate, mode of operation and frame format must be set up once before any serial reception can
be done. If synchronous operation is used, the clock on the XCKn pin will be used as transfer
clock.
The Receiver starts data reception when it detects a valid start bit. Each bit that follows the start
bit will be sampled at the baud rate or XCKn clock, and shifted into the Receive Shift Register
until the first stop bit of a frame is received. A second stop bit will be ignored by the Receiver.
When the first stop bit is received, that is, a complete serial frame is present in the Receive Shift
Register, the contents of the Shift Register will be moved into the receive buffer. The receive
buffer can then be read by reading the UDRn I/O location.
The following code example shows a simple USART receive function based on polling of the
Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant
bits of the data read from the UDRn will be masked to zero. The USART has to be initialized
before the function can be used.
ATmega640/1280/1281/2560/2561
214
Related parts for ATmega1280R212
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
Microcontroller with 128K bytes In-system programmable flash, 8 MHz, power supply =2.7 - 5.5V
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
8-bit Microcontroller with 128K Bytes In-System Programmable Flash
Manufacturer:
ATMEL Corporation
Datasheet:
Part Number:
Description:
IC AVR MCU 2.4GHZ XCEIVER 64QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ATMEGA644/AT86RF230 40-DIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
BUNDLE ATMEGA644P/AT86RF230 QFN
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
BUNDLE ATMEGA644P/AT86RF230 TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU ATMEGA1281/AT86RF230 64-TQFP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
MCU, 8BIT, AVR, 16K FLASH, 28PDIP
Manufacturer:
Atmel
Datasheet:
Part Number:
Description:
Microcontroller Modules MCU CARD BIGAVR6 100P W/ ATMEGA2560
Manufacturer:
mikroElektronika