ATmega1280R212 Atmel Corporation, ATmega1280R212 Datasheet - Page 195
ATmega1280R212
Manufacturer Part Number
ATmega1280R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1280R212
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
86
Spi
5
Twi (i2c)
1
Uart
4
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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21. SPI – Serial Peripheral Interface
2549N–AVR–05/11
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the
ATmega640/1280/1281/2560/2561 and peripheral devices or between several AVR devices.
The ATmega640/1280/1281/2560/2561 SPI includes the following features:
•
•
•
•
•
•
•
•
USART can also be used in Master SPI mode, see
The Power Reduction SPI bit, PRSPI, in
page 50 must be written to zero to enable SPI module.
Figure 21-1. SPI Block Diagram
Note:
The interconnection between Master and Slave CPUs with SPI is shown in
196. The system consists of two shift Registers, and a Master clock generator. The SPI Master
initiates the communication cycle when pulling low the Slave Select SS pin of the desired Slave.
Full-duplex, Three-wire Synchronous Data Transfer
Master or Slave Operation
LSB First or MSB First Data Transfer
Seven Programmable Bit Rates
End of Transmission Interrupt Flag
Write Collision Flag Protection
Wake-up from Idle Mode
Double Speed (CK/2) Master SPI Mode
1. Refer to
/2/4/8/16/32/64/128
DIVIDER
Figure 1-1 on page
ATmega640/1280/1281/2560/2561
(1)
2, and
“PRR0 – Power Reduction Register 0” on page 56
Table 13-6 on page 79
“USART in SPI Mode” on page
for SPI pin placement.
Figure 21-2 on page
232.
195
on
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