ATmega1280R212 Atmel Corporation, ATmega1280R212 Datasheet - Page 166
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ATmega1280R212
Manufacturer Part Number
ATmega1280R212
Description
Manufacturer
Atmel Corporation
Specifications of ATmega1280R212
Flash (kbytes)
128 Kbytes
Max. Operating Frequency
16 MHz
Max I/o Pins
86
Spi
5
Twi (i2c)
1
Uart
4
Adc Channels
16
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Crypto Engine
AES
Sram (kbytes)
8
Eeprom (bytes)
4096
Operating Voltage (vcc)
1.8 to 3.6
Timers
6
Frequency Band
700/800/900MHz
Max Data Rate (mb/s)
1
Antenna Diversity
No
External Pa Control
Yes
Power Output (dbm)
10
Receiver Sensitivity (dbm)
-110
Receive Current Consumption (ma)
9.0
Transmit Current Consumption (ma)
18 at 5dBm
Link Budget (dbm)
120
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17.11.33 TIMSK1 – Timer/Counter 1 Interrupt Mask Register
17.11.34 TIMSK3 – Timer/Counter 3 Interrupt Mask Register
17.11.35 TIMSK4 – Timer/Counter 4 Interrupt Mask Register
17.11.36 TIMSK5 – Timer/Counter 5 Interrupt Mask Register
2549N–AVR–05/11
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 5 – ICIEn: Timer/Countern, Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector (see
• Bit 3 – OCIEnC: Timer/Countern, Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
• Bit 2 – OCIEnB: Timer/Countern, Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare B Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
Bit
(0x6F)
Read/Write
Initial Value
Bit
(0x71)
Read/Write
Initial Value
Bit
(0x72)
Read/Write
Initial Value
Bit
(0x73)
Read/Write
Initial Value
See “Accessing 16-bit Registers” on page 138.
“Interrupts” on page
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
“Interrupts” on page
“Interrupts” on page
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ATmega640/1280/1281/2560/2561
105) is executed when the ICFn Flag, located in TIFRn, is set.
ICIE1
ICIE3
ICIE4
ICIE5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
105) is executed when the OCFnC Flag, located in
105) is executed when the OCFnB Flag, located in
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCIE1C
OCIE3C
OCIE4C
OCIE5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCIE1B
OCIE3B
OCIE4B
OCIE5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE1A
OCIE3A
OCIE4A
OCIE5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOIE1
TOIE3
TOIE4
TOIE5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIMSK1
TIMSK3
TIMSK4
TIMSK5
166
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