AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 45

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

6.3
6.4
6.5
6.6
6.7
7734P–AVR–08/10
ADC Noise Reduction Mode
Power-down Mode
Standby Mode
Power Reduction Register
Minimizing Power Consumption
tus Register – ACnCON. This will reduce power consumption in Idle mode. If the ADC is enabled, a
conversion starts automatically when this mode is entered.
When the SM2..0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC Noise Reduc-
tion mode, stopping the CPU but allowing the ADC, the External Interrupts, Timer/Counter (if their clock
source is external - T0 or T1) and the Watchdog to continue operating (if enabled). This sleep mode basi-
cally halts clk
This improves the noise environment for the ADC, enabling higher resolution measurements. If the ADC
is enabled, a conversion starts automatically when this mode is entered. Apart from the ADC Conversion
Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out Reset, a Timer/Counter inter-
rupt, an SPM/EEPROM ready interrupt, an External Level Interrupt on INT2:0 can wake up the MCU
from ADC Noise Reduction mode.
When the SM2..0 bits are written to 010, the SLEEP instruction makes the MCU enter Power-down mode.
In this mode, the External Oscillator is stopped, while the External Interrupts and the Watchdog continue
operating (if enabled). Only an External Reset, a Watchdog Reset, a Brown-out Reset, a PSC Interrupt, an
External Level Interrupt on INT2:0 can wake up the MCU. This sleep mode basically halts all generated
clocks, allowing operation of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the changed level
must be held for some time to wake up the MCU. Refer to
When waking up from Power-down mode, there is a delay from the wake-up condition occurs until the
wake-up becomes effective. This allows the clock to restart and become stable after having been stopped.
The wake-up period is defined by the same CKSEL fuses that define the Reset Time-out period, as
described in
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the SLEEP
instruction makes the MCU enter Standby mode. This mode is identical to Power-down with the excep-
tion that the Oscillator is kept running. From Standby mode, the device wakes up in six clock cycles.
The Power Reduction Register, PRR, provides a method to stop the clock to individual peripherals to
reduce power consumption. The current state of the peripheral is frozen and the I/O registers can not be
read or written. Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module, which is done
by clearing the bit in PRR, puts the module in the same state as before shutdown.
A full predictable behavior of a peripheral is not guaranteed during and after a cycle of stopping and start-
ing of its clock. So its recommended to stop a peripheral before stopping its clock with PRR register.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall power
consumption. In all other sleep modes, the clock is already stopped.
There are several issues to consider when trying to minimize the power consumption in an AVR con-
trolled system. In general, sleep modes should be used as much as possible, and the sleep mode should be
“Clock Sources” on page
I/O
, clk
CPU
, and clk
FLASH
, while allowing the other clocks to run.
28.
“External Interrupts” on page 82
AT90PWM81
for details.
45