AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 261

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

21.7.14
21.8
21.8.1
7734P–AVR–08/10
Serial Downloading
Reading the Calibration Byte
Serial Programming Algorithm
The algorithm for reading the Calibration byte is as follows (refer to
256
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while RESET is
pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET
is set low, the Programming Enable instruction needs to be executed first before program/erase operations
can be executed. NOTE, in
all parts use the SPI pins dedicated for the internal SPI interface.
Figure 21-7.
Notes:
When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation
(in the Serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip
Erase operation turns the content of every memory location in both the Program and EEPROM arrays into
0xFF.
Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods for the
serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f
High: > 2 CPU clock cycles for f
When writing serial data to the AT90PWM81, data is clocked on the rising edge of SCK.
1.
2.
3.
4.
for details on Command and Address loading):
A: Load Command “0000 1000”.
B: Load Address Low Byte, 0x00.
Set OE to “0”, and BS1 to “1”. The Calibration byte can now be read at DATA.
Set OE to “1”.
2.
1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the XTAL1
2. V
pin.
CC
Serial Programming and Verify
- 0.3V < AVCC < V
Table 21-13 on page
MOSI_A
MISO_A
SCK_A
ck
ck
CC
< 12 MHz, 3 CPU clock cycles for f
< 12 MHz, 3 CPU clock cycles for f
+ 0.3V, however, AVCC should always be within 1.8 - 5.5V
XTAL1
RESET
GND
(1)
254, the pin mapping for SPI programming is listed. Not
AVCC
VCC
+1.8 - 5.5V
+1.8 - 5.5V
“Programming the Flash” on page
ck
ck
(2)
>= 12 MHz
>= 12 MHz
AT90PWM81
261