AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 39

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

5.5.2
7734P–AVR–08/10
CLKPR – Clock Prescaler Register
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is
only updated when the other bits in CLKPR are simultaneously written to zero. CLKPCE is cleared by
hardware four cycles after it is written or when the CLKPS bits are written. Rewriting the CLKPCE bit
within this time-out period does neither extend the time-out period, nor clear the CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the AT90PWM81 and will always read as zero.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal system clock.
These bits can be written run-time to vary the clock frequency to suit the application requirements. As the
divider divides the master clock input to the MCU, the speed of all synchronous peripherals is reduced
when a division factor is used. The division factors are given in
To avoid unintentional changes of clock frequency, a special write procedure must be followed to change
the CLKPS bits:
Interrupts must be disabled when changing prescaler setting in order not to disturb the procedure.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed, the
CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to “0011”, giving a
division factor of eight at start up. This feature should be used if the selected clock source has a higher fre-
quency than the maximum frequency of the device at the present operating conditions. Note that any value
can be written to the CLKPS bits regardless of the CKDIV8 Fuse setting. The Application software must
ensure that a sufficient division factor is chosen if the selected clock source has a higher frequency than
the maximum frequency of the device at the present operating conditions. The device is shipped with the
CKDIV8 Fuse programmed.
Table 5-10.
Bit
Read/Write
Initial Value
1.
2.
CLKPS3
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to
zero.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
0
0
0
0
0
0
0
0
Clock Prescaler Select
CLKPCE
R/W
CLKPS2
7
0
0
0
0
0
1
1
1
1
R
6
–
0
CLKPS1
0
0
1
1
0
0
1
1
R
5
–
0
R
4
–
0
CLKPS0
0
1
0
1
0
1
0
1
CLKPS3
R/W
3
Table
CLKPS2
See Bit Description
R/W
2
5-10.
Clock Division Factor
CLKPS1
R/W
1
AT90PWM81
128
16
32
64
1
2
4
8
CLKPS0
R/W
0
CLKPR
39