AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet
AT90PWM161
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AT90PWM161 Summary of contents
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Features • High Performance, Low Power AVR ® 8-bit Microcontroller • Advanced RISC Architecture – 131 Powerful Instructions - Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation – ...
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Special Microcontroller Features – Low Power Idle, Noise Reduction, and Power Down Modes – Power On Reset and Programmable Brown Out Detection – Flag Array in bit-programmable I/O space (3 bytes) – In-System Programmable via SPI Port – Internal ...
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Pin Configurations Figure 2-1. 7734P–AVR–08/10 20 Pin Packages AT90PWM81 3 ...
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Figure 2-2. (ACMP3_OUT_A/SS/CLKO) PD0 (ACPM1_OUT/PSCIN2/XTAL1) PE1 AT90PWM81 4 32-Pin Packages AT90PWM81 QFN 32 5 (PSCOUT20) PB1 3 (INT0/PSCOUT21) PB2 4 VCC 5 GND PD5 (AMP0-/ADC7) 22 PE3/AREF/ADC6 21 AGND 20 ...
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Table 2-1. MNEMONIC GND AGND VCC AVCC AREF CLKO RESET# OCD XTAL1 XTAL2 MISO MOSI SCK SS INTn Tn PSCOUTxn PSCINx PSCOUT0n PSCINr ACMPn ACMPMn ACMPM ACOMPn_OUT AMPn- AMPn+ ADCn 7734P–AVR–08/10 : Alternate functions description NAME, FUNCTION & ALTERNATE FUNCTION ...
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Table 2-2. Port PB0 PE0 PD0 PB1 PB2 VCC GND PE1 PE2 PD1 PD2 PD3 PB3 PB4 PD4 PB5 AVCC AGND PD5 PD6 PB6 PD7 PB7 2.1 Pin Descriptions 2.1.1 VCC Digital supply voltage. 2.1.2 GND Ground. 2.1.3 Port B ...
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Port D (PD7..PD0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port D output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port D ...
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AVR CPU Core 3.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calcula- tions, ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typical ALU operation, two operands are output from the Register File, ...
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Note that the Status Register is updated after all ALU operations, as specified in the Instruction Set Refer- ence. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. ...
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General Purpose Register File The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve the required performance and flexibility, the following input/output schemes are supported by the Register File: • One 8-bit output ...
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Y-register Z-register In the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 3.6 Stack Pointer The Stack is mainly used for storing temporary data, for ...
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Figure 3-4. Figure 3-5 tion using two register operands is executed, and the result is stored back to the destination register. Figure 3-5. 3.8 Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate ...
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There are basically two types of interrupts. The first type is triggered by an event that sets the interrupt flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to exe- cute the interrupt ...
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C Code Example _SEI(); /* set Global Interrupt Enable */ _SLEEP(); /* enter sleep, waiting for interrupt */ /* note: will enter sleep before any pending interrupt(s) */ 3.8.2 Interrupt Response Time The interrupt execution response for all the enabled ...
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Memories This section describes the different memories in the AT90PWM81. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the AT90PWM81 fea- tures an EEPROM Memory for data storage. All ...
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The AT90PWM81 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only ...
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Figure 4-3. 4.3 EEPROM Data Memory The AT90PWM81 contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least ...
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The EEPROM Address Registers – EEARH and EEARL Bit Read/Write Initial Value • Bits 15..9 – Reserved Bits These bits are reserved bits in the AT90PWM81 and will always read as zero. • Bits 8..0 – EEAR8..0: EEPROM Address ...
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Bits 5..4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits The EEPROM Programming mode bit setting defines which programming action that will be triggered when writing EEWE possible to program data in one atomic operation (erase the ...
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Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the EEPROM Master Write Enable will time-out interrupt routine accessing the EEPROM is interrupting another EEPROM access, the EEAR or EEDR Register ...
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The order the different bits and registers should be accessed is: 1 Write EEPAGE in EECR (loading of temporary EEPROM buffer is enabled) 2 Write the address bits needed to address bytes within a page into EEARL 3 Write data ...
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Table 4-4. High Fuse Byte RSTDISBL DWEN SPIEN WDTON EESAVE BOOTSZ1 BOOTSZ0 BOOTRST Notes: Table 4-5. Low Fuse Byte CKDIV8 CKOUT SUT1 SUT0 CKSEL3 CKSEL2 CKSEL1 CKSEL0 Note: The status of the Fuse bits is not affected by Chip Erase. ...
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Code examples The following code examples show one assembly and one C function for writing to the EEPROM. The examples assume that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during execution of ...
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The next code examples show assembly and C functions for reading the EEPROM. The examples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned char ...
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I/O Memory The I/O space definition of the AT90PWM81 is shown in All AT90PWM81 I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the ...
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System Clock and Clock Options The AT90PWM81 provides a large number of clock sources. Those can be divided in two categories: internal and external. After reset, CKSEL Fuses select one clock source. Once the device is running, software clock ...
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CPU Clock – clk CPU The CPU clock is routed to parts of the system concerned with operation of the AVR core. Examples of such modules are the General Purpose Register File, the Status Register and the Data memory ...
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Table 5-1. Device Clocking Options Select Device Clocking Option External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (3.0 - 8.0 MHz) External Crystal/Ceramic Resonator (8.0 - 16.0 MHz) External Crystal/Ceramic Resonator (8.0 - 16.0 MHz) Note: The various ...
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The switch between 8 MHz and 1 MHz is done by the CKRC81 bit in MCUCR register. See trol Register – MCUCR” on page 41 CSEL configurations. At reset, the CKRC81 bit is initialised with the value compatible with CKSEL ...
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RC Oscillator calibration at Factory The RC oscillator is calibrated at 3V, 25°C for an 8MHz target frequency with an Accuracy +/- 1%. The corresponding value OSCAL (@Amb.) is stored in the signature row and automatically loaded in the ...
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The Oscillator can operate in three different modes, each optimized for a specific frequency range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in Table 5-6. CKSEL3..1 CSEL3..1 100 101 110 111 Notes: The ...
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External Clock To drive the device from this external clock source, CLKI should be driven as shown in the device on an external clock, the CKSEL Fuses or CSEL field must be programmed as shown in 5-1 on page ...
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The PLL is locked on the source oscillator which must remains close to 8 MHz to assure proper lock of the PLL. Both internal RC Oscillator and PLL are switched off in Power-down and Standby sleep modes Table 5-9. Start-up ...
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Dynamic Clock Switch 5.3.1 Features AT90PWM81 provides a powerful dynamic clock switch that allows users to turn on and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be enabled or disabled asynchro- ...
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When ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switching’ com- mand is entered, the selected configuration provided by the CLKSELR register is latched for each targeted clock source. ‘Recover System Clock Source’ command enables the code recovering ...
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It will be better to run this sequence once the interrupts disabled. The user (code) has the responsibility of the clock switching sequence. Here is a “light” C-code that describes such a sequence of ...
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System Clock Prescaler 5.4.1 Features The AT90PWM81 system clock can be divided by setting the Clock Prescaler Register – CLKPR. This feature can be used to decrease power consumption when the requirement for processing power is low. This can ...
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CLKPR – Clock Prescaler Register Bit Read/Write Initial Value • Bit 7 – CLKPCE: Clock Prescaler Change Enable The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE bit is only ...
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Table 5-10. CLKPS3 5.5.3 PLL Control and Status Register – PLLCSR Bit $29 ($29) Read/Write Initial Value • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the AT90PWM81 ...
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Bit 1 – PLLE: PLL Enable When the PLLE is set, the PLL is started and if not yet started the internal RC Oscillator is started as PLL reference clock. If PLL is selected as a system clock source ...
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Bits 3:0 – CLKC3:0: Clock Control Bits These bits define the command to provide to the ‘Clock Switch’ module. The special write procedure must be followed to change the CLKC bits 41.). 1. Write the Clock ...
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Bits 3:0 – CSEL3:0: Clock Source Select CSEL bits are initialized with the values of CKSEL Fuse bits. In case of ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switch’ command, CSEL field gets back the code ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. ...
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Register – ACnCON. This will reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automatically when this mode is entered. 6.3 ADC Noise Reduction Mode When the SM2..0 bits are written to 001, the ...
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All functions not needed should be disabled. In particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 6.7.1 Analog ...
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For analog input pins, the digital input buffer should be disabled at all times. An analog signal level close input pin can cause significant current even in active mode. Digital input buffers can be CC ...
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Bit 7 - PRPSC2: Power Reduction PSC2 Writing a logic one to this bit reduces the consumption of the PSC2 by stopping the clock to this module. When waking up the PSC2 again, the PSC2 should be re initialized ...
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System Control and Reset 7.1 System Control overview 7.1.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector ...
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Figure 7-1. BODLEVEL [2..0] Table 7-1. Symbol V POT V RST t RST Notes: 1. Values are guidelines only.. 2. The Power-on Reset will not work unless the supply voltage has been below V 7.1.3 Power-on Reset A Power-on Reset ...
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Figure 7-2. Figure 7-3. 7.1.4 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see guaranteed to generate a reset. When the applied signal reaches the ...
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Brown-out Detection AT90PWM81 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger level ...
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Figure 7-5. 7.1.6 Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t on operation ...
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Bit 2 – BORF: Brown-out Reset Flag This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset writing a logic zero to the flag. • Bit 1 – EXTRF: External ...
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DAC is used. To reduce power consumption in Power-down mode, the user can avoid the four conditions above to ensure that the reference is turned off before entering Power-down mode. 7.3.2 Voltage Reference Characteristics Table 7-4. Symbol ...
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In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer. One example is to limit the maximum time allowed for ...
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WDT_off: C Code Example void WDT_off(void Note: Note: If the Watchdog is accidentally enabled, for example by a runaway pointer or brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the code ...
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Assembly Code Example WDT_Prescaler_Change: ; Turn off global interrupt cli ; Reset Watchdog Timer wdr ; Start timed sequence lds r16, WDTCSR ori sts WDTCSR, r16 ; -- ; Set new prescaler(time-out) value = 64K cycles (~0.5 s) ldi sts ...
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Bit 6 - WDIE: Watchdog Interrupt Enable When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt is enabled. If WDE is cleared in combination with this setting, the Watchdog ...
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Table 7-6. WDP3 AT90PWM81 60 Watchdog Timer Prescaler Select Number of WDT Oscillator WDP2 WDP1 WDP0 ...
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Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM81. For a general explanation of the AVR interrupt handling, refer to 8.1 Interrupt Vectors in AT90PWM81 Table 8-1. Vector No ...
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This is also the case if the Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 8-2. BOOTRST 1 1 ...
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When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2K bytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and ...
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Moving Interrupts Between Application and Boot Space The MCU Control Register controls the placement of the Interrupt Vector table. 8.1.2 MCU Control Register – MCUCR ...
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Assembly Code Example Move_interrupts: C Code Example void Move_interrupts(void 7734P–AVR–08/10 ; Enable change of Interrupt Vectors ldi r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ldi r16, (1<<IVSEL) out MCUCR, r16 ret /* Enable ...
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I/O-Ports 9.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. description of one I/O-port pin, here generically called Pxn. Figure 9-2. Note: 9.2.1 Configuring the Pin Each port pin consists of three register bits: ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Figure 9-3. Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the clock is high, as indicated by the shaded region ...
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Assembly Code Example ... ; Define pull-ups and set outputs high ; Define directions for ...
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Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. port pin control signals from the simplified riding signals may not be present in all port pins, but the figure serves as a ...
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Table 9-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 9-3. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • PSCOUT22/ICP1/ADC9 – Bit 7 ...
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ADC5/ACMP2/INT1/SCK – Bit 5 ADC5, Analog to Digital Converter, input channel 5 ACMP2, Analog Comparator 2 Positive Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with ...
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Table 9-4 9-5 on page Table 9-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Table 9-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO The alternate pin configuration is as follows ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 9-6. Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: • ADC10/PSCINrA – Bit 7 ...
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ADC1/ACMP2_OUT, Bit 3 ADC1, Analog to Digital Converter, input channel 1. ACMP2_OUT, Analog Comparator 2 Output. • ADC0/ACMP1, Bit 2 ADC0, Analog to Digital Converter, input channel 0 ACMP1, Analog Comparator 1 Positive Input. Configure the port pin as ...
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Table 9-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 9.3.4 Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 9-9. Port Pin PE2 PE1 PE0 The alternate pin ...
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ACMP1M, Analog Comparator 1 Negative Input. Configure the port pin as input with the internal pull-up switched off to avoid the digital port function from interfering with the function of the Analog Comparator. PCSINr, PSCR Digital Input. • XTAL1/PSCIN2/ACMP1_OUT – ...
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Register Description for I/O-Ports 9.4.1 Port B Data Register – PORTB Bit Read/Write Initial Value 9.4.2 Port B Data Direction Register – DDRB Bit Read/Write Initial Value 9.4.3 Port B Input Pins Address – PINB Bit Read/Write Initial Value ...
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Port E Data Direction Register – DDRE Bit Read/Write Initial Value 9.4.9 Port E Input Pins Address – PINE Bit Read/Write Initial Value 7734P–AVR–08/ – – – – ...
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External Interrupts The External Interrupts are triggered by the INT2:0 pins. Observe that, if enabled, the interrupts will trig- ger even if the INT2:0 pins are configured as outputs. This feature provides a way of generating a software interrupt. ...
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External Interrupt Mask Register – EIMSK Bit Read/Write Initial Value • Bits 2..0 – INT2 – INT0: External Interrupt Request Enable When an INT2 – INT0 bit is written to one and the I-bit in the ...
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Reduced 16-bit Timer/Counter1 The 16-bit Timer/Counter unit allows accurate program execution timing (event management). The main features are: • Clear Timer on Compare Match (Auto Reload) • One Input Capture Unit • Input Capture Noise Cancelerr • External Event ...
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Figure 11-1. Note: 11.1.1 Registers The Timer/Counter (TCNT1), and Input Capture Register (ICR1) are all 16-bit registers. Special proce- dures must be followed when accessing the 16-bit registers. These procedures are described in the section “Accessing 16-bit Registers” on page ...
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Definitions The following definitions are used extensively throughout the section: BOTTOM MAX TOP 11.2 Accessing 16-bit Registers The TCNT1, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit ...
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Assembly Code Examples C Code Examples Note: The assembly code example returns the TCNT1 value in the r17:r16 register pair important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions ...
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TIM16_ReadTCNT1: ; Save global interrupt flag in r18,SREG ; Disable interrupts cli ; Read TCNT1 into r17:r16 in r16,TCNT1L in r17,TCNT1H ; Restore global interrupt flag out SREG,r18 ret C Code Example unsigned int TIM16_ReadTCNT1( void ) { unsigned char ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
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External Clock Source An external clock source applied to the T1/T0 pin can be used as Timer/Counter clock (clk T1/T0 pin is sampled once every system clock cycle by the pin synchronization logic. The synchronized (sampled) signal is then ...
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Signal description (internal signals): Count Clear clk TOP BOTTOM The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H) containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower eight bits. ...
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Figure 11-4. When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alternatively on the Analog Comparator output (ACO), and this change confirms to the setting of the edge detector, a capture will be ...
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Both the Input Capture pin (ICP1) and the Analog Comparator 1 output (AC1O) inputs are sampled using the same technique as for the T1 pin However, when the noise canceler is enabled, additional logic is inserted before the edge detector, ...
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However, combined with the timer overflow interrupt that automatically clears the TOV1 Flag, the timer resolution can be increased by software. There are no special cases to consider in the Nor- mal mode, a new counter value can ...
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Figure 11-6. TCNTn Figure 11-7 Figure 11-7. (clk TCNTn 7734P–AVR–08/10 Timer/Counter Timing Diagram, no Prescaling clk I/O clk Tn (clk /1) I/O TOP - 1 ICFn shows the count sequence close to MAX in various modes.. Timer/Counter Timing Diagram, no ...
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Timer/Counter Register Description 11.8.1 Timer/Counter1 Control Register B – TCCR1B Bit Read/Write Initial Value • Bit 7 – ICNC1: Input Capture Noise Canceler Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler ...
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Table 11-2. CS12 external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of ...
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Bit 7, 6 – Res: Reserved Bits These bits are unused bits in the AT90PWM81, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and ...
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Power Stage Controller – (PSCn) The Power Stage Controller is a high performance waveform controller. The AT90PWM81 includes one PSC2 block. 12.1 Features • PWM waveform generation function (2 complementary programmable outputs) • Dead time control • Standard mode ...
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PSC Description Figure 12-1. Note: The principle of the PSC is based on the use of a counter (PSC counter). This counter is able to count up and count down from and to values stored in registers according to ...
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PSC2 Distinctive Feature Figure 12-2. Note: PSC2 has two supplementary outputs PSCOUT22 and PSCOUT23. Thanks to a first selector PSCOUT22 can duplicate PSCOUT20 or PSCOUT21. Thanks to a second selector PSCOUT23 can duplicate PSCOUT20 or PSCOUT21. The Output Matrix ...
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Signal Description Figure 12-3. Note: 12.4.1 Input Description Table 12-1. Name OCRnRB[11 :0] OCRnSB[11 :0] OCRnRA[1 1:0] OCRnSA[11 :0] AT90PWM81 102 PSC External Block View CLK PLL CLK I/O SYnI n StopOut 12 OCRnR B[11:0] 12 OCRnSB[11:0] 12 OCRnR ...
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Name OCRnRB[1 5:12] CLK I/O CLK PLL SYnIn StopIn Note: Table 12-2. Name PSCINn from 1st A C PSCINnA from 2nd A C 12.4.2 Output Description Table 12-3. Name PSCOUTn0 PSCOUTn1 PSCOUTn2 (PSC2 only) PSCOUTn3(P SC2 only) Table 12-4. Name ...
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Note: 12.5 Functional Description 12.5.1 Waveform Cycles The waveform generated by PSC can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTn0 output and part A of PSC. The part of this waveform is ...
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Running Mode Description Waveforms and length of output signals are determined by Time Parameters (DT0, OT0, DT1, OT1) and by the running mode. Four modes are possible : – Four Ramp mode – Two Ramp mode – One Ramp ...
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Figure 12-7. PSC Counter PSCOUTn0 PSCOUTn1 PSCOUTn0 and PSCOUTn1 signals are defined by On-Time 0, Dead-Time 0, On-Time 1 and Dead-Time 1 values with : On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * ...
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Figure 12-8. PSC Counter PSCOUTn0 PSCOUTn1 On-Time 0 = (OCRnRAH/L - OCRnSAH/L) * 1/Fclkpsc On-Time 1 = (OCRnRBH/L - OCRnSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRnSAH 1/Fclkpsc Dead-Time 1 = (OCRnSBH/L - OCRnRAH/L) * 1/Fclkpsc Note: 12.5.2.4 ...
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Figure 12-9. On-Time OCRnSAH/L * 1/Fclkpsc On-Time (OCRnRBH/L - OCRnSBH 1/Fclkpsc Dead-Time = (OCRnSBH/L - OCRnSAH/L) * 1/Fclkpsc PSC Cycle = 2 * (OCRnRBH 1/Fclkpsc Note: ...
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Fifty Percent Waveform Configuration When PSCOUTn0 and PSCOUTn1 have the same characteristics, it’s possible to configure the PSC in a Fifty Percent mode. When the PSC is in this configuration, it duplicates the OCRnSBH/L and OCRnRBH/L registers in OCRnSAH/L ...
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Enhanced Resolution Lamp Ballast applications need an enhanced resolution down to 50Hz. The method to improve the normal resolution is based on Flank Width Modulation (also called Fractional Divider). Cycles are grouped into frames of 16 cycles. Cycles are ...
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According to the ramp mode and the enhanced resolution mode (defined by PBFMn1:0), the average fre- quency deviation Δf can take three different values: These values are applied according to the running mode and the enhanced resolution mode as per ...
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Table 12-6. Distribution of fb2 in the modulated frame Fraction al Divider ( While ‘X’ in the table for each row, a ...
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The waveform frequency is defined by the following equation: 12.7.2.2 Enhanced Mode The Enhanced Mode uses the previously described method to generate a high resolution frequency. 12-13 gives an example of FWM with PBFMn1:0 = 00. Figure 12-13. Enhanced Mode, ...
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According to PSC n Input A Control Register (see Section “PSC n Input A Control Register – PFRCnA”, page 140), PSC n input A can act as a Retrigger or Fault input. Each part can be triggered ...
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Figure 12-15. PSC Input Module B PSCINn AC2 O: Analog Comparator Output PSCINnA AC3 O:Analog Comparator Output 12.8.1 PSC Retrigger Behavior versus PSC running modes In centered mode, Retrigger Inputs have no effect. In two ramp or four ramp mode, ...
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Figure 12-16. PSCOUTn0 retrograde by PSCn Input A (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Note: Figure 12-17. PSCOUTn0 retriggered by PSCn Input A (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input A (high level) ...
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Figure 12-18. PSCOUTn1 retriggered by PSCn Input B (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Note: Figure 12-19. PSCOUTn1 retriggered by PSCn Input B (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input B (high level) ...
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Figure 12-20. Burst Generation PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 12.8.4 PSC Input Configuration The PSC Input Configuration is done by programming bits in configuration registers. 12.8.4.1 Filter Enable If the “Filter Enable” bit ...
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If PELEVnx bit set, the significant edge of PSCn Input rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - 4-ramp mode, PSCn Input A is ...
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PSC Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 12-22. PSCn behavior versus PSCn Input A in Fault Mode 1 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is ...
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PSC Input Mode 2: Stop signal, Execute Opposite Pulse and Wait Figure 12-24. PSCn behavior versus PSCn Input A in Fault Mode 2 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is take ...
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PSC Input Mode 3: Stop signal, Execute Opposite Pulse while Fault active Figure 12-26. PSCn behavior versus PSCn Input A in Mode 3 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSC Input A is ...
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PSC Input Mode 4: Deactivate outputs without changing timing. Figure 12-28. PSC behavior versus PSCn Input A or Input B in Mode 4 DT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 12-29. PSC behavior versus PSCn ...
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Used in Fault mode 5, PSCn Input A or PSCn Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 12.14 PSC Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. Figure 12-31. PSC behavior versus PSCn Input A ...
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PSC Input Mode 8: Edge Retrigger PSC Figure 12-33. PSC behavior versus PSCn Input A in Mode 8 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurrence of significative edge of retriggering input. ...
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PSC Input Mode 9: Fixed Frequency Edge Retrigger PSC Figure 12-35. PSC behavior versus PSCn Input A in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurrence of significative edge ...
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PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Deactivate Output Figure 12-37. PSC behavior versus PSCn Input A in Mode 14 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the ...
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Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes. Table 12-8. Input Mode Number : 1 ...
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PSC2 Outputs 12.19.1 Output Matrix PSC2 has an output matrix which allow in 4 ramp mode to program a value of PSCOUT20 and PSCOUT21 binary value for each ramp. Table 12-9. PSCOUT20 PSCOUT21 PSCOUT2m takes the value given in ...
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Analog Synchronization PSC generates a signal to synchronize the sample and hold or the ADC start; synchronization is manda- tory for measurements. This signal can be selected between all falling or rising edge of PSCn0 or PSCn1 outputs as ...
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PSC Synchronization Note : In AT90PWM81, this feature is not relevant and PRUN2, PARUN2 are stuck at zero PSC can be synchronized together. In this case, two waveform alignments are possible: • The waveforms are center ...
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According to the architecture of the PSC synchronization which build a “daisy-chain on the PSC run sig- nal” between the three PSC, only the fault event (mode 7) which is able to “stop” the PSC through the PRUN bits is ...
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List of Interrupt Vector Each PSC provides 3 interrupt vectors • PSCn EC (End of Cycle): When enabled and when a match with OCRnRB occurs • PSCn EEC (End of Enhanced Cycle): When enabled and when a match with ...
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Table 12-12. PSYNCn1 • Bit 3 – POEN2D : PSCOUT23 Output Enable (PSC2 only) When this bit is clear, second I/O pin affected to PSCOUT23 acts as a standard port. When this bit is set, second ...
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Output Compare SB Register – OCRnSBH and OCRnSBL Bit Read/Write Initial Value 12.25.5 Output Compare RB Register – OCRnRBH and OCRnRBL Bit Read/Write Initial Value Note : according to PSC number. The Output Compare ...
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Bit 4:3 – PMODEn1: 0: PSC n Mode Select the mode of PSC. Table 12-13. PMODEn1 • Bit 2 – POPn: PSC n Output Polarity If this bit is cleared, the PSC outputs are active ...
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Table 12-14. Analog signal synchronization or Input Blanking Mode Selection PASDLKn2 PASDLKn1 • Bit 4- PBFMn1: Balance Flank Width Modulation, bit 1 Defines the Flank Width Modulation, together with PBFMn0 bit in ...
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Bit 3– PELEVnA1: PSC n Input Select for part A Together with PELEVnA0, defines active edge or level on PSC part A. Table 12-16. PELEVnA1 • Bit 2– PELEVnB1: PSC n Input Select for part ...
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Bit 0– PISELnB1: PSC n Input Select for part B Together with PISELnB0, defines active signal on PSC part B. Table 12-19. PISELnB1 12.25.8 Analog Synchronization Delay Register – PASDLYn Bit Read/Write Initial Value The ...
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Table 12-20. PPREn1 • Bit 5 – PBFMn0 : Balance Flank Width Modulation bit 0 Defines the Flank Width Modulation, together with PBFMn1 bit in PCNFEn register. See Table 12-15 on page 137 • Bit 4 – ...
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The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way. • Bit 7 – PCAEnx : PSC n Capture Enable Input ...
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Table 12-21. PRFMnx3:0 1010b 1011b 1100b 1101b 1110b 1111b 12.25.12 PSC 2 Input Capture Register – PICR2H and PICR2L Bit Read/Write Initial Value • Bit 7 – PCSTn : PSC Capture Software Trig bit Set this bit to trigger off ...
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Bit 4 – POMV2B0: Output Matrix Output B Ramp 0 This bit gives the state of the PSCOUT21 (and/or PSCOUT23) during ramp 0 • Bit 3 – POMV2A3: Output Matrix Output A Ramp 3 This bit gives the state ...
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PSC2 Interrupt Flag Register – PIFR2 Bit Read/Write Initial Value • Bit 7 – POACnB : PSC n Output B Activity This bit is set by hardware each time the output PSCOUTn1 changes from from ...
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Table 12-22. PRNn1 • Bit 0 – PEOPn: End Of PSC n Interrupt This bit is set by hardware when PSC n achieves its whole cycle. Must be cleared by software by writing a one to ...
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PSCRV fuse bit. In this second case, PSCOUT20 & PSCOUT21 keep the forced state until PSOC2 register is written. If PSC2RBA fuse equals 1 (unprogrammed), PSCOUT22 & PSCOUT23 keep a standard port behavior. If PSC2RBA fuse equals ...
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Reduced Power Stage Controller – (PSCR) The Reduced Power Stage Controller is a high performance waveform controller. 13.1 Features • PWM waveform generation function (2 complementary programmable outputs) • Dead time control • Standard mode bit ...
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PSCR Description Figure 13-1. The principle of the PSCR is based on the use of a counter (PSCR counter). This counter is able to count up and count down from and to values stored in registers according to the ...
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Output Polarity The polarity “active high” or “active low” of the PSCR outputs is programmable. All the timing diagrams in the following examples are given in the “active high” polarity. 13.4 Signal Description Figure 13-2. 13.4.1 Input Description Table ...
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Name OCRrSA[11 :0] CLK I/O CLK PLL Table 13-2. Name PSCINr from Analog Comparator PSCINrA PSCINrB 13.4.2 Output Description Table 13-3. Name PSCOUTr0 PSCOUTr1 Table 13-4. Name PICRr [11:0] IRQPSCr PSCrASY AT90PWM81 150 Description Compare Value which Set Signal on ...
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Functional Description 13.5.1 Waveform Cycles The waveform generated by PSCR can be described as a sequence of two waveforms. The first waveform is relative to PSCOUTr0 output and part A of PSC. The part of this waveform is sub- ...
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The waveform frequency is defined by the following equation: 13.5.2.1 Four Ramp Mode In Four Ramp mode, each time in a cycle has its own definition Figure 13-4. PSC Counter PSCOUTn0 PSCOUTn1 The input clock of PSCR is given by ...
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Two Ramp Mode In Two Ramp mode, the whole cycle is divided in two moments One moment for PSCr0 description with OT0 which gives the time of the whole moment One moment for PSCr1 description with OT1 which gives ...
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Figure 13-6. PSC Counter PSCOUTn0 PSCOUTn1 On-Time 0 = (OCRrRAH/L - OCRrSAH/L) * 1/Fclkpsc On-Time 1 = (OCRrRBH/L - OCRrSBH/L) * 1/Fclkpsc Dead-Time 0 = (OCRrSAH 1/Fclkpsc Dead-Time 1 = (OCRrSBH/L - OCRrRAH/L) * 1/Fclkpsc Note: 13.5.3 ...
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Figure 13-7. Software PSC The software can stop the cycle before the end to update the values and restart a new PSCR cycle. 13.6.1 Value Update Synchronization New timing values or PSCR output configuration can be written during the PSCR ...
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Figure 13-8. PSCINr AC1 O: Analog Comparator Output PSCINrA PSCINrB 13.8.1 PSCR Retrigger Behavior versus PSCR running modes In two ramp or four ramp mode, Retrigger Inputs cause the end of the corresponding cycle ...
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Figure 13-9. PSCOUTn0 PSCOUTn1 PSCn Input A (falling edge) PSCn Input A (rising edge) Note: Figure 13-10. PSCOUTr0 retriggered by PSCr Input A (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) Note: 13.8.3 Retrigger ...
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Figure 13-11. PSCOUTr1 retriggered by PSCr Input B (Edge Retriggering) PSCOUTn0 PSCOUTn1 PSCn Input B (falling edge) PSCn Input B (rising edge) Note: Figure 13-12. PSCOUTr1 retriggered by PSCr Input B (Level Acting) PSCOUTn0 PSCOUTn1 PSCn Input B (high level) ...
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Figure 13-13. Burst Generation PSCOUTn0 PSCOUTn1 PSCn Input A (high level) PSCn Input A (low level) 13.8.4 PSCR Input Configuration The PSCR Input Configuration is done by programming bits in configuration registers. 13.8.4.1 Filter Enable If the “Filter Enable” bit ...
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If PELEV0x bit set, the significant edge of PSCr Input rising (edge modes) or the active level is high (level modes) and vice versa for unset/falling/low - 4-ramp mode, PSCr Input A is ...
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PSCR Input Mode 1: Stop signal, Jump to Opposite Dead-Time and Wait Figure 13-14. PSCr behavior versus PSCr Input A in Fault Mode 1 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSCR Input A is ...
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PSCR Input Mode 2: Stop signal, Execute Opposite Dead-Time and Wait Figure 13-16. PSCr behavior versus PSCr Input A in Fault Mode 2 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSCR Input A is take ...
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PSCR Input Mode 3: Stop signal, Execute Opposite while Fault active Figure 13-18. PSCr behavior versus PSCr Input A in Mode 3 DT0 OT0 DT1 OT1 PSCOUTn0 PSCOUTn1 PSC Input A PSC Input B PSCR Input A is taken ...
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PSCR Input Mode 4: Deactivate outputs without changing timing. Figure 13-20. PSCR behavior versus PSCr Input A or Input B in Mode 4 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A or PSCn Input B Figure 13-21. PSCR behavior versus ...
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Used in Fault mode 5, PSCr Input A or PSCr Input B act indifferently on On-Time0/Dead-Time0 or on On-Time1/Dead-Time1. 13.14 PSCR Input Mode 6: Stop signal, Jump to Opposite Dead-Time and Wait. Figure 13-23. PSCR behavior versus PSCr Input A ...
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PSCR Input Mode 8: Edge Retrigger PSC Figure 13-25. PSCR behavior versus PSCr Input A in Mode 8 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is modulated by the occurrence of significative edge of retriggering input. ...
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PSCR Input Mode 9: Fixed Frequency Edge Retrigger PSC Figure 13-27. PSCR behavior versus PSCr Input A in Mode 9 DT0 OT0 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the occurrence of significative edge ...
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PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate Output Figure 13-29. PSCR behavior versus PSCr Input A in Mode 14 DT0 OT0 DT1 PSCOUTn0 PSCOUTn1 PSCn Input A The output frequency is not modified by the ...
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Available Input Mode according to Running Mode Some Input Modes are not consistent with some Running Modes. So the table below gives the input modes which are valid according to running modes. Table 13-6. Input Mode Number : 1 ...
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This signal can be selected between all falling or rising edge of PSCr0 or PSCr1 outputs. 13.20 Interrupt Handling List of interrupt sources: • Counter reload (end of On Time 1) • PSCR Input event (active edge or at the ...
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Interrupts This section describes the specifics of the interrupt handling as performed in AT90PWM81. 13.22.1 List of Interrupt Vector The PSCR provides 3 interrupt vectors • PSC0EC (End of Cycle): When enabled and when a match with OCRrRB occurs ...
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Bit 5:4 – PSYNC01:0: Synchronization Out for ADC Selection) Select the polarity and signal source for generating a signal which will be sent to the ADC for synchronization. Table 13-10. PSYNC01 • Bit 3 – ...
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Output Compare RB Register – OCR0RBH and OCR0RBL Bit Read/Write Initial Value The Output Compare Registers RA, RB, SA and SB contain a 12-bit value that is continuously compared with the PSCR counter value. A match can be used ...
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Table 13-11. PMODE01 • Bit 2 – POP0: PSCR Output Polarity If this bit is cleared, the PSCR outputs are active Low. If this bit is set, the PSCR outputs are active High. • Bit 1 ...
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Bit 5- PBFM01: Balance Flank Width Modulation, bit 1 Defines the Flank Width Modulation, together with PBFM00 bit. Table 13-13. PBFM01 • Bit 4 – PAOC0B : PSCR Asynchronous Output Control B When this ...
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The Input Control Registers are used to configure the 2 PSC’s Retrigger/Fault block A & B. The 2 blocks are identical, so they are configured on the same way. • Bit 7 – PCAE0x : PSCR Capture Enable Input Part ...
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Table 13-14. PRFM0x3:0 1010b 1011b 1100b 1101b 1110b 1111b 13.23.10 PSCR Input Capture Register – PICR0H and PICR0L Bit Read/Write Initial Value • Bit 7 – PCST0 : PSCR Capture Software Trig bit Set this bit to trigger off a ...
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Bit 2 – Reserved • Bit 1– PEOEPE0 : PSCR End Of Enhanced Cycle Interrupt Enable When this bit is set, an interrupt is generated when PSC reduced reaches the end of the 15th PSC cycle. This allows to ...
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Table 13-15. PRN01 • Bit 0 – PEOP0: End Of PSCR Interrupt This bit is set by hardware when PSCR achieves its whole cycle. Must be cleared by software by writing a one to its location. ...
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Serial Peripheral Interface – SPI: 14.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The interconnection between Master and Slave CPUs with SPI is shown in sists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the desired ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden accord- ing to Table page 71. Table 14-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize ...
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Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. 7734P–AVR–08/10 ...
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Assembly Code Example SPI_SlaveInit: ; Set MISO output, all others input ldi out ; Enable SPI ldi out ret SPI_SlaveReceive: ; Wait for reception complete sbis SPSR,SPIF rjmp SPI_SlaveReceive ; Read received data and return in ret C Code Example ...
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The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous with the master clock generator. When the SS pin is driven high, the SPI slave will immediately reset the send and receive logic, and drop ...
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Figure 14-3. Figure 14-4. 14.5 SPI registers 14.5.1 SPI Control Register – SPCR Bit Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR ...
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Bit 5 – DORD: Data Order When the DORD bit is written to one, the LSB of the data word is transmitted first. When the DORD bit is written to zero, the MSB of the data word is transmitted ...
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SPI Status Register – SPSR Bit Read/Write Initial Value • Bit 7 – SPIF: SPI Interrupt Flag When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in SPCR is set and ...
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Voltage Reference and Temperature Sensor 15.1 Features • Accurate Voltage Reference of 2.56V • Internal Temperature Sensor • Possibility for Runtime Compensation of Temperature Drift in Both Voltage Reference and On Chip Oscillators • Low Power Consumption 15.2 On ...
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Figure 15-1. Reference Circuitry Aref SW0 AVc c VPTAT Vbg BG Ref erence BG Calibr ation Fus es BG Calibr ation Reg isters BGCC R, BGCRR AT90PWM81 has an On-chip temperature sensor for monitoring the die temperature. A voltage Propor- ...
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Register Description 15.3.1 BGCCR – Bandgap Calibration Current Register Bit Read/Write Initial Value • Bit 7:4 – Res: Reserved Bit This bit is reserved for future use. • Bit 3:0 – BGCC3:0: BG Calibration of PTAT Current These bits ...
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Illustration of Vbg as a function of temperature. Figure 15-2. 1.5 BGCRR is used to move the top of the Vbg curve to the center of the temperature range of interest 1.0 0.5 -40 -20 -0 15.4 Temperature Measurement The ...
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Table 15-1. When the voltage reference equals 2.56V, the conversion result has approxi- mately a 1 LSB/°C (or 2.5 mV/°C) correlation to temperature and the typical accuracy of the temperature measurement is +/- 10°C after offset calibration. Table ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin ACMPx and negative pin ACMPM or ACMPMx. 16.1 Features • 3 Analog Comparators • High Speed analog Comparators • +/-25mV or +/-10mV or 0 Hysteresis • ...
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Figure 16-1. ACMP1_OUT ACMP1 ACMPM1 ACMP2_OUT ACMP2 ACMPM2 ACMP3_OUT_A ACMP3_OUT ACMP3 ACMPM3 ACMPM Notes: 7734P–AVR–08/10 Analog Comparator Block Diagram AC1 OE AC1 OI Band Gap AC2 OE AC2 OI AC1 Band Gap AC3 OEA AC3 OI ...
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Figure 16-2. 16.3 Shared pins between Analog Comparator and ADC Several Analog comparators input pins can also be used as ADC inputs possible to measure the comparison voltages. However, when a comparator input is selected as the ...
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Analog Comparator 1Control Register – AC1CON Bit Read/Write Initial Value • Bit 7– AC1EN: Analog Comparator 1 Enable Bit Set this bit to enable the analog comparator 1. Clear this bit to disable the analog comparator 1. • Bit ...
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Analog Comparator 2 Control Register – AC2CON Bit Read/Write Initial Value • Bit 7– AC2EN: Analog Comparator 2 Enable Bit Set this bit to enable the analog comparator 2. Clear this bit to disable the analog comparator 2. • ...
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Analog Comparator 3 Control Register – AC3CON Bit Read/Write Initial Value • Bit 7– AC3EN: Analog Comparator 3 Enable Bit Set this bit to enable the analog comparator 3. Clear this bit to disable the analog comparator 3. • ...
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Analog Comparator n Extended Control Register – ACnECON Bit Read/Write Initial Value • Bit 7..6– Reserved • Bit 5– AC1OI: Analog Comparator n Output Invert Set this bit to invert the analog comparator n output . Clear this bit ...