AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 177

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

13.23.10
13.23.11
7734P–AVR–08/10
PSCR Input Capture Register – PICR0H and PICR0L
PSCR Interrupt Mask Register – PIM0
Table 13-14.
• Bit 7 – PCST0 : PSCR Capture Software Trig bit
Set this bit to trigger off a capture of the PSCR counter. When reading, if this bit is set it means that the
capture operation was triggered by PCST0 setting otherwise it means that the capture operation was trig-
gered by a PSCR input.
The Input Capture is updated with the PSCR counter value each time an event occurs on the enabled
PSCR input pin (or optionally on the Analog Comparator output) if the capture function is enabled (bit
PCAE0x in PFRC0x register is set).
The Input Capture Register is 12-bit in size. To ensure that both the high and low bytes are read simultane-
ously when the CPU accesses these registers, the access is performed using an 8-bit temporary high byte
register (TEMP). This temporary register is shared by all the other 16-bit or 12-bit registers.
Bit
Read/Write
Initial Value
• Bit 7- 5 – Reserved
• Bit 4 – PEVE0B : PSCR External Event B Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block B gener-
ates also an interrupt.
• Bit 3 – PEVE0A : PSCR External Event A Interrupt Enable
When this bit is set, an external event which can generates a capture from Retrigger/Fault block A gener-
ates also an interrupt.
Bit
Read/Write
Initial Value
PRFM0x3:0
1010b
1011b
1100b
1101b
1110b
1111b
7
-
R
0
7
PCST0
R
0
Level Sensitivity and Fault Mode Operation
Description
Reserved (do not use)
PSCR Input Mode 14: Fixed Frequency Edge Retrigger PSCR and Deactivate
Output
Reserved (do not use)
6
-
R
0
6
–
R
0
5
-
R
0
5
–
R
0
4
PEVE0B
R/W
0
0
4
–
R
PICR0[7:0]
3
PEVE0A
R/W
0
3
PICR0[11:8]
R
0
2
-
R
0
2
R
0
1
0
PEOEPE0 PEOPE0
R
1
R
0
AT90PWM81
0
R/W
0
0
R
0
PIM0
PICR0H
PICR0L
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