AT90PWM161 Atmel Corporation, AT90PWM161 Datasheet - Page 222

• Manufacturer Part Number: AT90PWM161
• Manufacturer: Atmel Corporation

Specifications of AT90PWM161

• Flash (kbytes): 16 Kbytes
• Pin Count: 20
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 20
• Ext Interrupts: 3
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 11
• Adc Resolution (bits): 10
• Adc Speed (ksps): 125
• Analog Comparators: 3
• Resistive Touch Screen: No
• Dac Channels: 1
• Dac Resolution (bits): 10
• Temp. Sensor: Yes
• Crypto Engine: No
• Sram (kbytes): 0.25
• Eeprom (bytes): 512
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 1
• Output Compare Channels: 8
• Input Capture Channels: 1
• Pwm Channels: 6
• 32khz Rtc: No
• Calibrated Rc Oscillator: Yes

To ensure an accurate result in case of large voltage change, the amplifier input needs to have a quite sta-
ble sampled input value during at least 4 Amplifier synchronization clock periods.
Amplified conversions can be synchronized to PSC events (See
“Synchronization Source Description in
One/Two/Four Ramp Modes” on page 133
and
“Synchronization Source Description in Centered Mode”
on page
134) or to the internal clock CK
equal to eighth the ADC clock frequency. In case the syn-
ADC
chronization is done by the ADC clock divided by 8, this synchronization is done automatically by the
ADC interface in such a way that the sample-and-hold occurs at a specific phase of CK
. A conversion
ADC2
initiated by the user (i.e., all single conversions, and the first free running conversion) when CK
is
ADC2
low will take the same amount of time as a single ended conversion (13 ADC clock cycles from the next
prescaled clock cycle). A conversion initiated by the user when CK
is high will take 14 ADC clock
ADC2
cycles due to the synchronization mechanism.
The normal way to use the amplifier is to select a synchronization clock via the AMPxTS1:0 bits in the
AMPxCSR register. Then the amplifier can be switched on, and the amplification is done on each syn-
chronization event. The amplification is done independently of the ADC.
In order to start an amplified Analog to Digital Conversion on the amplified channel, the ADMUX must
be configured as specified on
Table 17-4 on page
217.
The ADC starting is done by setting the ADSC (ADC Start conversion) bit in the ADCSRB register.
Until the conversion is not achieved, it is not possible to start a conversion on another channel.
On AT90PWM81, conversion takes advantage of the amplifier characteristics to ensure minimum conver-
sion time.
As soon as a conversion is requested thanks to the ADSC bit, the Analog to Digital Conversion is started.
In order to have a better understanding of the functioning of the amplifier synchronization, a timing dia-
gram example is shown
Figure
17-15.
In case the amplifier output is modified during the sample phase of the ADC, the on-going conversion is
aborted and restarted as soon as the output of the amplifier is stable as shown
Figure
17-16.
The only precaution to take is to be sure that the trig signal (PSC) frequency is lower than ADCclk/4.
It is also possible to auto trigger conversion on the amplified channel. In this case, the conversion is
started at the next amplifier clock event following the last auto trigger event selected thanks to the ADTS
bits in the ADCSRB register. In auto trigger conversion, the free running mode is not possible unless the
ADSC bit in ADCSRA is set by soft after each conversion.
Figure 17-15. Amplifier synchronization timing diagram with change on analog input signal.
Figure 17-16. Amplifier synchronization timing diagram: behavior when ADSC is set when theampli-
fier output is changing.
The block diagram of the two amplifiers is shown on
Figure
17-17.
AT90PWM81
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