AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet - Page 132

• Manufacturer Part Number: AT89C51CC03
• Manufacturer: Atmel Corporation

Specifications of AT89C51CC03

• Flash (kbytes): 64 Kbytes
• Max. Operating Frequency: 40 MHz
• Cpu: 8051-12C
• Max I/o Pins: 37
• Spi: 1
• Uart: 1
• Can: 1
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 62.5
• Sram (kbytes): 2.25
• Eeprom (bytes): 2048
• Self Program Memory: API
• Operating Voltage (vcc): 3.0 to 5.5
• Timers: 4
• Isp: UART/CAN
• Watchdog: Yes

Master Mode
Slave Mode
Transmission Formats
132
AT89C51CC03
When the Master device transmits data to the Slave device via the MOSI line, the Slave
device responds by sending data to the Master device via the MISO line. This implies
full-duplex transmission with both data out and data in synchronized with the same clock
(Figure 59).
Figure 59. Full-Duplex Master-Slave Interconnection
The SPI operates in Master mode when the Master bit, MSTR
is set. Only one Master SPI device can initiate transmissions. Software begins the trans-
mission from a Master SPI Module by writing to the Serial Peripheral Data Register
(SPDAT). If the shift register is empty, the Byte is immediately transferred to the shift
register. The Byte begins shifting out on MOSI pin under the control of the serial clock,
SCK. Simultaneously, another Byte shifts in from the Slave on the Master’s MISO pin.
The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSCR
becomes set. At the same time that SPIF becomes set, the received Byte from the Slave
is transferred to the receive data register in SPDAT. Software clears SPIF by reading
the Serial Peripheral Status register (SPSCR) with the SPIF bit set, and then reading the
SPDAT.
The SPI operates in Slave mode when the Master bit, MSTR
cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave
device must be set to’0’. SS must remain low until the transmission is complete.
In a Slave SPI Module, data enters the shift register under the control of the SCK from
the Master SPI Module. After a Byte enters the shift register, it is immediately trans-
ferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an
overflow condition, Slave software must then read the SPDAT before another Byte
enters the shift register
ister) at least one bus cycle before the Master SPI starts a transmission. If the write to
the data register is late, the SPI transmits the data already in the shift register from the
previous transmission.
Software can select any of four combinations of serial clock (SCK) phase and polarity
using two bits in the SPCON: the Clock Polarity (CPOL
(CPHA
effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 60 and Figure 61).
The clock phase and polarity should be identical for the Master SPI device and the com-
municating Slave device.
1.
2.
3.
4.
Clock Generator
4
). CPOL defines the default SCK line level in idle state. It has no significant
The SPI Module should be configured as a Master before it is enabled (SPEN set). Also,
The SPI Module should be configured as a Slave before it is enabled (SPEN set).
The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock
Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’).
SPI
the Master SPI should be configured before the Slave SPI.
speed.
Master MCU
8-bit Shift register
(3)
. A Slave SPI must complete the write to the SPDAT (shift reg-
MOSI
SCK
SS
MISO
VDD
MOSI
MISO
SCK
VSS
SS
8-bit Shift register
Slave MCU
(2)
(4)
(1)
, in the SPCON register is
) and the Clock Phase
, in the SPCON register
4182O–CAN–09/08