AT89C51CC03 Atmel Corporation, AT89C51CC03 Datasheet - Page 10
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AT89C51CC03
Manufacturer Part Number
AT89C51CC03
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT89C51CC03.pdf
(7 pages)
2.AT89C51CC03.pdf
(198 pages)
3.AT89C51CC03.pdf
(32 pages)
4.AT89C51CC03.pdf
(27 pages)
Specifications of AT89C51CC03
Flash (kbytes)
64 Kbytes
Max. Operating Frequency
40 MHz
Cpu
8051-12C
Max I/o Pins
37
Spi
1
Uart
1
Can
1
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
62.5
Sram (kbytes)
2.25
Eeprom (bytes)
2048
Self Program Memory
API
Operating Voltage (vcc)
3.0 to 5.5
Timers
4
Isp
UART/CAN
Watchdog
Yes
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Manufacturer
Quantity
Price
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Quasi-Bidirectional Port
Operation
10
AT89C51CC03
write the new byte back to the latch. These Read-Modify-Write instructions are directed
to the latch rather than the pin in order to avoid possible misinterpretation of voltage
(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of
an external bipolar transistor can not rise above the transistor’s base-emitter junction
voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU
to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather
than the pins returns the correct logic-one value.
Port 1, Port 2, Port 3 and Port 4 have fixed internal pull-ups and are referred to as
"quasi-bidirectional" Ports. When configured as an input, the pin impedance appears as
logic one and sources current in response to an external logic zero condition. Port 0 is a
"true bidirectional" pin. The pins float when configured as input. Resets write logic one to
all Port latches. If logical zero is subsequently written to a Port latch, it can be returned
to input conditions by a logical one written to the latch.
Note:
Logical zero-to-one transitions in Port 1, Port 2, Port 3 and Port 4 use an additional pull-
up (p1) to aid this logic transition (see Figure 4.). This increases switch speed. This
extra pull-up sources 100 times normal internal circuit current during 2 oscillator clock
periods. The internal pull-ups are field-effect transistors rather than linear resistors. Pull-
ups consist of three p-channel FET (pFET) devices. A pFET is on when the gate senses
logical zero and off when the gate senses logical one. pFET #1 is turned on for two
oscillator periods immediately after a zero-to-one transition in the Port latch. A logical
one at the Port pin turns on pFET #3 (a weak pull-up) through the inverter. This inverter
and pFET pair form a latch to drive logical one. pFET #2 is a very weak pull-up switched
on whenever the associated nFET is switched off. This is traditional CMOS switch con-
vention. Current strengths are 1/10 that of pFET #3.
Figure 4. Internal Pull-Up Configurations
Note:
OUTPUT DATA
INPUT DATA
READ PIN
Port latch values change near the end of Read-Modify-Write instruction cycles. Output
buffers (and therefore the pin state) update early in the instruction after Read-Modify-
Write instruction cycle.
Port 2 p1 assists the logic-one output for memory bus cycles.
2 Osc. PERIODS
VCC
p1(1)
n
VCC
p2
4182O–CAN–09/08
VCC
p3
P1.x
P2.x
P3.x
P4.x