AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 595

• Manufacturer Part Number: AT32UC3A0128AU
• Manufacturer: Atmel Corporation

Specifications of AT32UC3A0128AU

• Flash (kbytes): 128 Kbytes
• Pin Count: 144
• Max. Operating Frequency: 66 MHz
• Cpu: 32-bit AVR
• # Of Touch Channels: 32
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 109
• Ext Interrupts: 109
• Usb Transceiver: 1
• Usb Speed: Full Speed
• Usb Interface: Device + OTG
• Spi: 6
• Twi (i2c): 1
• Uart: 4
• Ssc: 1
• Ethernet: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 384
• Resistive Touch Screen: No
• Dac Channels: 2
• Dac Resolution (bits): 16
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 32
• Self Program Memory: YES
• External Bus Interface: 1
• Dram Memory: sdram
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 85
• I/o Supply Class: 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Operating Voltage (vcc): 3.0-3.6 or (1.65-1.95+3.0-3.6)
• Fpu: No
• Mpu / Mmu: Yes / No
• Timers: 10
• Output Compare Channels: 16
• Input Capture Channels: 6
• Pwm Channels: 13
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

32058K AVR32-01/12
30.8.2.20
Offset:
Register Name:
Access Type:
Reset Value:
• CH_EN: Channel Enabled
If set, the DMA channel is currently enabled.
If cleared, the DMA channel does no longer transfer data.
• CH_ACTIVE: Channel Active
If set, the DMA channel is currently trying to source USB data.
If cleared, the DMA channel is no longer trying to source USB data.
When a USB data transfer is completed, this bit is automatically reset.
• EOT_STA: End of USB Transfer Status
Set by hardware when the completion of the usb data transfer has closed the dma transfer. It is valid only if
BUFF_CLOSE_EN=1.
This bit is automatically cleared when read by software.
• EOCH_BUFF_STA: End of Channel Buffer Status
Set by hardware when the Channel Byte Count downcounts to zero.
This bit is automatically cleared when read by software.
• DESC_LD_STA: Descriptor Loaded Status
Set by hardware when a Descriptor has been loaded from the HSB bus.
This bit is automatically cleared when read by software.
31
23
15
0
0
–
7
–
USB Device DMA Channel X Status Register (UDDMAX_STATUS)
DESC_LD_
STA
30
22
14
ru
0
0
–
6
0
EOCH_BUFF_
STA
29
21
13
ru
0
0
–
5
0
0x031C + (X - 1) . 0x10
UDDMAX_STATUS, X in [1..6]
Read/Write
0x00000000
EOT_STA
28
20
12
ru
0
0
–
4
0
CH_BYTE_CNT
CH_BYTE_CNT
ru
ru
27
19
11
0
0
–
3
–
26
18
10
0
0
–
2
–
CH_ACTIVE
rwu
25
17
0
0
9
–
1
0
AT32UC3A
CH_EN
rwu
24
16
0
0
8
–
0
0
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