AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 574
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
For isochronous, bulk and interrupt OUT endpoints:
This bit is inactive (cleared) for isochronous, bulk and interrupt IN endpoints.
• RXSTPI: Received SETUP Interrupt Flag
For control endpoints, set by hardware to signal that the current bank contains a new valid SETUP packet. This triggers an
EPXINT interrupt if RXSTPE = 1.
Shall be cleared by software (by setting the RXSTPIC bit) to acknowledge the interrupt and to free the bank.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means UNDERFI for isochronous IN/OUT
endpoints.
• UNDERFI: Underflow Interrupt Flag
For isochronous IN/OUT endpoints, set by hardware when an underflow error occurs. This triggers an EPXINT interrupt if
UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-length packet is then auto-
matically sent by the USB controller.
An underflow can also occur during OUT stage if the host sends a packet while the bank is already full. Typically, the CPU
is not fast enough. The packet is lost.
Shall be cleared by software (by setting the UNDERFIC bit) to acknowledge the interrupt.
This bit is inactive (cleared) for bulk and interrupt IN/OUT endpoints and it means RXSTPI for control endpoints.
• NAKOUTI: NAKed OUT Interrupt Flag
Set by hardware when a NAK handshake has been sent in response to an OUT request from the host. This triggers an
EPXINT interrupt if NAKOUTE = 1.
Shall be cleared by software (by setting the NAKOUTIC bit) to acknowledge the interrupt.
• NAKINI: NAKed IN Interrupt Flag
Set by hardware when a NAK handshake has been sent in response to an IN request from the host. This triggers an EPX-
INT interrupt if NAKINE = 1.
Shall be cleared by software (by setting the NAKINIC bit) to acknowledge the interrupt.
• OVERFI: Overflow Interrupt Flag
Set by hardware when an overflow error occurs. This triggers an EPXINT interrupt if OVERFE = 1.
For all endpoint types, an overflow can occur during OUT stage if the host attempts to write into a bank that is too small for
the packet. The packet is acknowledged and the Received OUT Data interrupt (RXOUTI) is raised as if no overflow had
occurred. The bank is filled with all the first bytes of the packet that fit in.
Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt and to free the bank.
Set by hardware at the same time as FIFOCON when the current bank is full. This triggers an EPXINT interrupt if
RXOUTE = 1.
Shall be cleared by software (by setting the RXOUTIC bit) to acknowledge the interrupt, what has no effect on the
endpoint FIFO.
The software then reads from the FIFO and clears the FIFOCON bit to free the bank. If the OUT endpoint is com-
posed of multiple banks, this also switches to the next bank. The RXOUTI and FIFOCON bits are updated by
hardware in accordance with the status of the next bank.
RXOUTI shall always be cleared before clearing FIFOCON.
AT32UC3A
574
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