AT32UC3A0128AU Atmel Corporation, AT32UC3A0128AU Datasheet - Page 519
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AT32UC3A0128AU
Manufacturer Part Number
AT32UC3A0128AU
Description
Manufacturer
Atmel Corporation
Datasheets
1.AT32UC3A0128.pdf
(98 pages)
2.AT32UC3A0128.pdf
(826 pages)
3.AT32UC3A0128.pdf
(377 pages)
4.AT32UC3A0128.pdf
(33 pages)
5.AT32UC3A0128.pdf
(159 pages)
6.AT32UC3A0128AU.pdf
(2 pages)
Specifications of AT32UC3A0128AU
Flash (kbytes)
128 Kbytes
Pin Count
144
Max. Operating Frequency
66 MHz
Cpu
32-bit AVR
# Of Touch Channels
32
Hardware Qtouch Acquisition
No
Max I/o Pins
109
Ext Interrupts
109
Usb Transceiver
1
Usb Speed
Full Speed
Usb Interface
Device + OTG
Spi
6
Twi (i2c)
1
Uart
4
Ssc
1
Ethernet
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
384
Resistive Touch Screen
No
Dac Channels
2
Dac Resolution (bits)
16
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
32
Self Program Memory
YES
External Bus Interface
1
Dram Memory
sdram
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 85
I/o Supply Class
3.0-3.6 or (1.65-1.95+3.0-3.6)
Operating Voltage (vcc)
3.0-3.6 or (1.65-1.95+3.0-3.6)
Fpu
No
Mpu / Mmu
Yes / No
Timers
10
Output Compare Channels
16
Input Capture Channels
6
Pwm Channels
13
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3A0128AU-U
Manufacturer:
ATMEL
Quantity:
4
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32058K AVR32-01/12
Figure 30-20. Example of an OUT Endpoint with 1 Data Bank
Figure 30-21. Example of an OUT Endpoint with 2 Data Banks
30.7.2.13.2 Detailed Description
30.7.2.14
RXOUTI
FIFOCON
RXOUTI
FIFOCON
OUT
OUT
Underflow
(bank 0)
DATA
(bank 0)
DATA
The data is read by the firmware, following the next flow:
If the endpoint uses several banks, the current one can be read by the firmware while the follow-
ing one is being written by the host. Then, when the firmware clears FIFOCON, the following
bank may already be ready and RXOUTI is set immediately.
This error exists only for isochronous IN/OUT endpoints. It raises the Underflow interrupt
(UNDERFI), what triggers an EPXINT interrupt if UNDERFE = 1.
An underflow can occur during IN stage if the host attempts to read from an empty bank. A zero-
length packet is then automatically sent by the USB controller.
•when the bank is full, RXOUTI and FIFOCON are set, what triggers an EPXINT interrupt if
•the firmware acknowledges the interrupt by clearing RXOUTI;
•the firmware can read the byte count of the current bank from BYCT to know how many bytes
•the firmware reads the data from the current bank by using the USB Pipe/Endpoint X FIFO
•the firmware frees the bank and switches to the next bank (if any) by clearing FIFOCON.
RXOUTE = 1;
to read, rather than polling RWALL;
Data register (USB_FIFOX_DATA), until all the expected data frame is read or the bank is
empty (in which case RWALL is cleared by hardware and BYCT reaches 0);
HW
ACK
HW
ACK
SW
read data from CPU
SW
BANK 0
NAK
OUT
read data from CPU
BANK 0
(bank 1)
DATA
SW
OUT
ACK
(bank 0)
DATA
HW
SW
HW
ACK
read data from CPU
SW
read data from CPU
AT32UC3A
BANK 1
SW
BANK 0
519
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